Functional Verification of Programmable Embedded Architectures: A Top-Down Approach by Prabhat MishraEnglish | PDF | 2005 | 186 Pages | ISBN : 0387261435 | 10.25 mb
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation.
