PathWave Advanced Design System (ADS) 2025 Update 2

Circuit Simulation

General
- Support ASM-HEMT model version 101.5.

Data Display

General
- (Beta Release) DDS Python APIs and related Data Display user interface were added as below:
. In the DDS Python module, the following were added:
.. APIs for editing advanced Trace Properties
.. APIs for arranging and changing the display ordering of objects
. In the DDS window, the following capabilities were added:
.. Adding/Editing Python Expressions directly on a page in a window
.. Refer to Python Equation Tool for details
- Improved initial display performance with markers and large traces on different pages.
- Added user-defined independent axis label to Smith Charts and Polar Plots.

Design & Tech Management

General
- Design Editing Python Module
. Updated Python documentation pages
. Added support for Ground Planes and Interconnects
. Added Python API to unarchive workspaces
. Added initial support for version control APIs enabling ability to request check-in and check-out designs and files
. Added support for SmartMount technology
. Added support for exporting Thermal Technology files
. Improved support (e.g. transform) for physical design objects (e.g. instances, shapes, etc.)
. Clarified support for editable or read-only collections in API
- Added sympy to ADS Python environment.
- ANN Python - Improved documentation and examples.

Design Cloud

General
- The Design Cloud Simulation Job window now includes a new Summary tab. This tab provides detailed information about jobs in one place, specifically displaying the cluster IDs of the main job and child jobs and their execution hostname.
- Users can now download partial results for terminated jobs in Design Cloud simulations. To enable this feature, set ENABLE_PARTIAL_RESULTS_DOWNLOAD=1 in the de_sim.cfg file located in $HOME/hpeesof/config . A download button will appear in the ADS Design cloud simulation window, allowing users to download and install the partial results of the terminated job.
- Python APIs to submit Design Cloud Simulations are now introduced and documented. To know more, you can open ADS and go to Help > Python API > Design Cloud.
EM - SIPro/PIPro/RFPro
- Design Cloud supports parallel simulations on Windows for Power Aware SI analysis.
RF Microwave
- Design Cloud supports parallel simulations when SP Output controller is used in the schematic.
- Design Cloud supports parallel simulations when Matlab Output controller is used in the schematic.
- Design Cloud supports implicit file references from DAC component. It is expected that user doesn't have to externally specify the files referred by DAC controller using a UPL file.

Design Editing and Layout

General
- The cover layers with 377-ohm termination impedance will be shown with a different pattern and color to distinguish it from metallic cover layers.
- The copy-paste operation can optionally preserve net names. A new preference was added to the Entry/Edit tab to support this option. For more information, refer Layout Preferences.
- Improved the performance of ground plane generation by approximately 33% faster.
- The Smart Mount Instance Editor''s context menu has been augmented to enable users to modify the mount layer and mount subtype.
- The Mirror command will display a warning dialog if smart mount instances are included in the selected set. This would allow users to exclude these components from mirroring, as mirroring smart mount components is often undesirable.
- Added a new AEL API, db_create_plane_from_child_shapes(), to create a plane composite object from a collection of shapes. This function replaces the now-deprecated db_convert_shapes_to_plane() function.
Design Import/Export
- The GDSII Exporter has been revised to warn the user if the design being exported contains elements on layers that are not mapped by the layer map file. For more information, refer GDSII Stream File Translator.
- The GDSII stream export dialog has a new option of Select/Deselect All layers.
- The Gerber Importer can support the Step and Repeat (SR) specification.

Design Kits

General
- PDK Builder has been deprecated in ADS 2025 Update 2.0, and will be removed in ADS 2026.
DemoKit mmWave
- The thermal substrate of DemoKit_mmWave has been updated to demonstrate orthotropic conductivity.

EM Simulation

General
- The keysight.ads.emtools Python module provides functionality to facilitate working with the EM tools. The API has been extended and documented. See ADS Main Window, Help > Python API > EM…
RFPro
- RFPro-FEM simulations with a 'sampled' frequency-dependent material are now supported. A new material can be defined in RFPro and override an existing material assignment.
- RFPro-Momentum simulation statistics (proj.sta) are now available on a new 'Statistics' tab in the Simulations window.
- 3D components can now be rotated arbitrarily.
SIPro/PIPro
- Trace Width visualization is implemented. Can be enabled in Modelling Options.
LTD Substrate Editor
- The editor now supports viewing/editing bounding area layers.
- The editor provides a way to view the decoded 'FOUNDRY_TECH' section (unavailable for an encrypted substrate).
Momentum
- The modeling approach to account for the 'damage k' regions side-by-side of conductors in advanced IC nodes has been refined.
- The low frequency stability of the Momentum uW-mode source used in calibration has been improved.
FEM
- Several mesh failures have been addressed.
Broadband Spice Model Generator
- New RFM output format has been added.

HSD

DDR/Memory
- Supports SIPro cell sweep in Memory Designer.
Serdes/Chiplet
- New Product: System Designer for USB:
. Supports USB4® Gen2, Gen3, Gen4(PAM3)
. Supports USB Compliance Tests
. Supports USB AMI model builder
- Supports USB4® v1 compliance test.
- Supports SIPro cell sweep in Chiplet PHY Designer.
- Supports New MIPI® C-PHYSM Waveform source.
- Supports InfiniiMax Probe model in Smart Probe.
- Improved AMI model builder:
. Provide optimization and adaptive equalization value into the Dataset
- S-Parameter toolkit enhancements:
. Automatic differential pair matching based on the port name