"Che l'ultimo - ora malinconicamente postumo - romanzo di Giampaolo Rugarli si intitoli 'Manuale di solitudine' assume inevitabilmente un valore simbolico, quasi a riassumere il suo intero percorso esistenziale e letterario; difficile infatti trovare un'insegna più pregnante del suo carattere, della tensione che segna la ricerca espressiva e contemporaneamente le scelte morali: d'altronde a questo titolo egli giunse, appunto, dopo aver scartato ogni altro descrittivo o referenziale. Se per un verso questo 'Manuale' completa il ciclo estremo, paradossale e grottesco, della sua narrativa, che esplora con dolente furore i desolati territori della disperazione, opponendo loro un'inarrendevole fiducia nella resistenza dell'etica; per l'altro riassume la sua avventura letteraria, intrapresa di fronte alla riconosciuta 'impossibilità di vivere' per riconquistare sulla pagina quanto era andato perduto nel corso del tempo, conservando intatto un radicale e inconsolabile pessimismo.

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After a brief introduction to low-power VLSI design, the design space of ASIP instruction set architectures (ISAs) is introduced with a special focus on important features for digital signal processing. Based on the degrees of freedom offered by this design space, a consistent ASIP design flow is proposed: this design flow starts with a given application and uses incremental optimization of the ASIP hardware, of ASIP coprocessors and of the ASIP software by using a top-down approach and by applying application-specific modifications on all levels of design hierarchy. A broad range of real-world signal processing applications serves as vehicle to illustrate each design decision and provides a hands-on approach to ASIP design. Finally, two complete case studies demonstrate the feasibility and the efficiency of the proposed methodology and quantitatively evaluate the benefits of ASIPs in an industrial context.

Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-design one's FPGAs and Computer- Aided Design (CAD) tools.

Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators. The programmable parts include micro-controllers and Digital Signal Processors (DSPs).

In April 1995, WINLAB (the Wireless Infonnation Network Lab­ oratory at Rutgers University) hosted the Fifth WINLAB Workshop on Third Generation Wireless Infonnation Networks. This workshop brings together a select group of experts interested in the future of Personal Communications, Mobile Computing and other services supported by wireless communications. As a sequel to Kluwer books on previous WINLAB workshops,l this volume assembles written versions of presentations of the Fifth Workshop. The last few years have been exciting for the field of wireless communications. The second generation systems that have absorbed our attention during those years are becoming commercial realities. Everyone is looking forward to PCS, especially in light of the recent auctions. We see an explosion of technical alternatives for meeting the demand for wireless communications. We also have applications in search of the best technologies rather than the reverse. The papers included provide new insights into many of the issues needing resolution for the successful introduction of the new services by the end of the decade. The authors represent views from both industry and universities from a number of nations. They are grouped into four main categories: Architecture, Radio Resource Management, Access, and Mobile Data, Mobile Networks.

Software Synthesis from Dataflow Graphs addresses the problem of generating efficient software implementations from applications specified as synchronous dataflow graphs for programmable digital signal processors (DSPs) used in embedded real- time systems. The advent of high-speed graphics workstations has made feasible the use of graphical block diagram programming environments by designers of signal processing systems. A particular subset of dataflow, called Synchronous Dataflow (SDF), has proven efficient for representing a wide class of unirate and multirate signal processing algorithms, and has been used as the basis for numerous DSP block diagram-based programming environments such as the Signal Processing Workstation from Cadence Design Systems, Inc., COSSAP from Synopsys® (both commercial tools), and the Ptolemy environment from the University of California at Berkeley.

Symbolic Boolean manipulation using binary decision diagrams (BDDs) has been successfully applied to a wide variety of tasks, particularly in very large scale integration (VLSI) computer-aided design (CAD). The concept of decision graphs as an abstract representation of Boolean functions dates back to the early work by Lee and Akers. In the last ten years, BDDs have found widespread use as a concrete data structure for symbolic Boolean manipulation. With BDDs, functions can be constructed, manipulated, and compared by simple and efficient graph algorithms. Since Boolean functions can represent not just digital circuit functions, but also such mathematical domains as sets and relations, a wide variety of CAD problems can be solved using BDDs.