Since the discovery in 1986 of high temperature superconductors by J. G. Bednorz and K. A. Müller, a considerable progress has been made and several important scientific problems have emerged. Within this NATO Advanced Study Institute our intention was to focus mainly on the controversial topic of the symmetry of the superconducting gap and given the very short coherence length, the role of fluctuations. The Institute on ‘The Gap Symmetry and Fluctuations in High- Superconductors’ took place in the “Institut d’Etudes Scientifiques de Cargèse” in Corsica, France, between 1 - 13 September 1997. The 110 participantsfrom 18 countries (yet 30 nationalities) including 23 full time lecturers, have spent two memorable weeks in this charming Mediterranean resort. All lecturers were asked to prepare pedagogical papers to clearly present the central physical idea behind specific model or experiment. The better understanding of physics of high temperature superconductivity is certainly needed to guide the development of applications of these materials in high and weak current devices.

For someone with a hammer the whole world looks like a nail. Within the last 10-13 years Binar·y Decision Diagmms (BDDs) have become the state-of-the-art data structure in VLSI CAD for representation and ma­ nipulation of Boolean functions. Today, BDDs are widely used and in the meantime have also been integrated in commercial tools, especially in the area of verijication and synthesis. The interest in BDDs results from the fact that the data structure is generally accepted as providing a good compromise between conciseness of representation and efficiency of manipulation. With increasing number of applications, also in non CAD areas, classical methods to handle BDDs are being improved and new questions and problems evolve and have to be solved. The book should help the reader who is not familiar with BDDs (or DDs in general) to get a quick start. On the other hand it will discuss several new aspects of BDDs, e.g. with respect to minimization and implementation of a package. This will help people working with BDDs (in industry or academia) to keep informed about recent developments in this area.

If you survey hardware design groups, you will learn that between 60% and 80% of their effort is dedicated to verification. This may seem unusually large, but I include in "verification" all debugging and correctness checking activities, not just writing and running testbenches. Every time a hardware designer pulls up a waveform viewer, he or she performs a verification task. With today’s ASIC and FPGA sizes and geometries, getting a design to fit and run at speed is no longer the main challenge. It is to get the right design, working as intended, at the right time. Unlike synthesizable coding, there is no particular coding style nor language required for verification. The freedom of using any l- guage that can be interfaced to a simulator and of using any features of that language has produced a wide array of techniques and approaches to verification. The continued absence of constraints and historical shortage of available expertise in verification, c- pled with an apparent under-appreciation of and under-investment in the verification function, has resulted in several different ad hoc approaches. The consequences of an informal, ill-equipped and understaffed verification process can range from a non-functional design requiring several re-spins, through a design with only a s- set of the intended functionality, to a delayed product shipment.