The intention of this book is to address a number of timely, performance-critical issues within the field of short-distance optical communications, from a circuit designer’s perspective. It discusses the major trade-offs the designer has to deal with in the development of monolithically integrated receivers in CMOS technologies. As such, it is based on Dr. Muller’s doctoral dissertation entitled “A Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit Optical Data Communications”, subm- ted to the School of Engineering of the École Polytechnique Fédérale de Lausanne (EPFL) in May 2006. The dissertation material has been enhanced by the presentation of a number of alternative design approaches and circuit topologies, providing exhaustive coverage of the state of the art in optical sho- distance receiver circuit design. The need for a new processor input/output (I/O) interface paradigm is dictated by ongoing te- nology scaling and the advent of multi-core systems. Indeed, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput, whereas the available bandwidth of the I/O interfaces is subject to much slower growth. Moving beyond - coming serial links to an optical data link paradigm for very short-distance (board-to-board and chip– chip communications allows for considerable I/O interface bandwidth enhancement. Fully integrated silicon CMOS receivers are considered to be the technology of choice to lead this solution to economic success, because monolithic integration results in lower volume-manufacturing cost, improved yield and reduced assembly and test expenses.

The increasing performance of smart microsystems merging sensors, signal processing and wireless communication promises to have a pervasive impact during the coming decade. These autonomous microsystems nd applications in sport evaluation, health care, environmental monitoring and automotive s- tems. They gather data from the physical world, convert them to electrical form, compensate for interfering variables or non-linearities, and either act - rectly on them or transfer it to other systems. Most often, these sensor systems are developed for a speci c application. This approach leads to a high rec- rent design cost. A generic front-end architecture, where only the sensors and the microcontroller software are customized to the selected application, would reduce the costs signi cantly. This work presents a new generic architecture for autonomous sensor nodes. The modular design methodology provides a exible way to build a complete sensor interface out of con gurable blocks. The settings of these blocks can be optimized according to the varying needs of the application. Furthermore, the system can easily be expanded with new building blocks. The modular system is illustrated in a Generic Sensor Interface Chip (GSIC) for capa- tive sensors. Many con guration settings adapt the interface to a broad range of applications. The GSIC is optimized for ultra low power consumption. It achieves an ON-state current consumption of 40?A.

À Rouen, dans ce quartier bourgeois, impossible de manquer la devanture rose des Bouchères. Depuis la rue, on peut entendre l'aiguisage des couteaux, les masses qui cognent la viande et les rires des trois femmes qui tiennent la boutique. Derrière le billot, elles arborent fièrement leurs ongles pailletés et leurs avant-bras musclés. Mais elles seules savent ce qui les lie : une enfance estropiée, une adolescence rageuse et un secret. …

In the market of wireless communication, high data-rate transmission and high spectral efficiency have been the trend. The IEEE 802.11 a/g standards working at 5GHz/2.4GHz ISM bands can support data rate up to 54Mbits/s using OFDM modulation. The newly proposed 802.11n technology now uses 64-QAM to achieve higher spectral efficiency. The DVB and many other systems will also use QAM for its data transmission.