VSD - Clock Tree Synthesis - Part 1
VSD - Clock Tree Synthesis - Part 1
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 241 MB | Duration: 3h 57m
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 241 MB | Duration: 3h 57m
VLSI - Building a chip is like building a city!!
What you'll learn
CTS Quality Checks (Skew, Power, Latency, etc.)
H-Tree
Quality Check of H-Tree
Clock Tree Buffering
Buffered H-Tree
H-Tree with uneven spread of Flops
Advanced H-Tree for Million Flops
Power Aware CTS (clock gating)
Static Timing Analysis with Clock Tree
Requirements
Individuals having Basic Knowledge of Electrical and Electronics
Description
Clock Tree Networks are Pillars and Columns of a Chip.
With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.
The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.
Who this course is for
Individuals keen to learn about VLSI and Chip World