Memory Controllers for Mixed-Time-Criticality Systems
Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs
Springer | Engineering | May 15 2016 | ISBN-10: 3319320939 | 202 pages | pdf | 7.89 mb
Springer | Engineering | May 15 2016 | ISBN-10: 3319320939 | 202 pages | pdf | 7.89 mb
Authors: Goossens, S., Chandrasekar, K., Akesson, B., Goossens, K.
Discusses power-constrained mixed-time-criticality systems and why they are complex to design and verify
Explains the concepts of predictability and composability and how they address the design and verification challenges of mixed-time-criticality systems
Provides an overview of the requirements of memory controllers in power-constrained mixed-time-criticality systems and discusses why current memory controllers struggle to satisfy them
This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.
Number of Illustrations and Tables
78 illustrations in colour
Topics
Circuits and Systems
Processor Architectures
Electronics and Microelectronics, Instrumentation
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