Cadence Virtuoso, Release Version ICADVM20.1 ISR31

2332454 Unable to resize a graph strip in Virtuoso Visualization and Analysis XL
2332071 Cannot change the test name in maestro view in ADE Explorer
2327724 The CSV file in which the setup is exported from the Results tab in ADE Assembler is not saved at the desired location
2327005 Wrong column header exporting CSV file from detail transpose
2326741 Virtuoso exits unexpectedly due to an internal application error
2326292 Running 'runsv' reports 'runams' instead of 'runsv'
2326286 Virtuoso exits unexpectedly when editing a figGroup
2325395 Create Via command violates shape boundary for polygonal shapes
2325056 Virtuoso exits unexpectedly when saving constraints cache
2324097 Virtuoso exits unexpectedly when launching Schematics XL
2324083 Virtuoso exits unexpectedly due to an internal application error
2323750 Padstacks are erroneously exported to CLF as bumps
2323703 Virtuoso exits unexpectedly due to a segmentation fault in ddtUpdateGraph in IC6.1.8 ISR12
2323562 Create Via command not following the correct purpose defined in layer1ExtraParams
2323534 Via not created by Auto Via command due to obstruction.
2323038 emir.conf file not written to the netlist directory for AMS EMIR run with the new EMIR UI
2322780 3X performance degradation observed during power grid generation as cover cell at initialization
2322703 5X performance degradation observed during power grid generation as FigGroup at initialization
2321972 The Chaining command takes up to 2 minutes to open the Options form
2321733 Virtuoso exits unexpectedly in ctuOaUpdate::registerOAShapeToBeDeleted
2321703 Virtuoso exits unexpectedly when deleting labels in Text Editor
2321436 Virtuoso exits unexpectedly when deleting labels in Text Editor
2321137 Virtuoso exits unexpectedly during Check and Save
2321080 Probe translation fails when device prefix is different for different devices of the same type
2319537 The Push Pre-Routes command ignores via blockages when there are floating wires in the design
2319127 Remove all instances of catch/throw from the code
2318879 Virtuoso exits unexpectedly when deleting labels in Text Editor
2317803 Virtuoso exits unexpectedly when using Design Intent
2317179 Checker does not consider full wire length to determine width direction when using the minOppExtension table
2316623 Auto Via command must reduce one edge by 1db to handle another offset correctly
2316506 Virtuoso exits unexpectedly when browsing Rapid Analog Prototype constraints
2316443 Unable to generate eadTechFile using the eadModelGen utility
2315205 minViaSpacing support for centerToCenter parameter does not work as expected
2314971 Expressions with extracted view net mapping in LSCS control mode evaluate into errors but evaluate successfully in ICRP mode
2314905 The simulation does not run on setting up a single individual fault in the ADE Assembler fault simulation setup
2314592 Virtuoso exits unexpectedly while processing a pop-up menu event
2313575 Improve handling of netlisting failures
2312572 Extractor claims there is no via definition with implant layer if extractVerifyWellSubstrateConnections is nil
2312347 Virtuoso exits unexpectedly after AMS Monte Carlo simulation completes
2312108 Updating library property bag using the FirstAccessLib trigger fails in ICADVM18.1
2311881 The Set Valid Layers form is distorted in IC6.1.8 but appears fine in IC6.1.7
2310932 Decap Fill places overlapping decaps
2309540 Add save statements for post layout signals used in expressions
2309431 Checker does not flag violations when using direction parameters with minOppExtension
2309277 Virtuoso exits unexpectedly during dbClose
2308056 Virtuoso exits unexpectedly during descend read
2307756 Virtuoso exits unexpectedly when saving constraints cache
2307603 A beta license is required to use the technology file in Voltus-Fi
2307296 Random netlist and simulation errors when run Size Over Corners
2306918 Incorrect pg_function exported for some pins
2306226 DesignSync options are ignored when creating a setup library view using the slaOpenOrCreateView function
2305135 Placement Planning throws an error when the Tap tab is hidden
2305117 SystemVerilog Netlister stops responding and causes Virtuoso to exit unexpectedly
2305014 Need an option to display all the active WSPs for a given layer
2304848 Virtuoso exits unexpectedly while cleaning up raw shape to fractured shapes mapping.
2304824 Virtuoso exits unexpectedly when saving constraints cache
2304346 Unable to resize a graph strip in Virtuoso Visualization and Analysis XL
2303971 pg_function is not being detected correctly
2303856 Fault simulation with sampling fails because fault statement has incomplete sample option
2303636 Setting CDS_USE_XVFB to 1 generates an xmsim: *E,STRPIN error that stops invoking the SimVision GUI in interactive mode.
2303616 Setting CDS_USE_XVFB to 1 generates an xmsim: *E,STRPIN error that stops invoking the SimVision GUI in interactive mode
2303562 Trunk trim generate wrong begin and end point of a pathSeg
2303178 Virtuoso stops responding when using leHiAssignNet command and Repeat Command is off in the Layout Editor Options form
2303148 SystemVerilog Netlister stops responding when using time literals to override CDF parameters
2302634 Unable to generate an AMS netlist when using pPar function in the parameter values for the specified instances
2302553 The Voltus-Fi GUI does not load any nets in the EM results window when vsaSetEMPlot and vsaLoadNets functions are used together
2302343 Expression evaluates for failed iteration of Monte Carlo run in LSCS run mode
2301963 Many config views are created with config sweep by LSCS in ADE
2301789 Virtuoso exits unexpectedly when evaluating the spectrumMeasurement expression from ADE Assembler
2301775 Allegro Import translator generates errors in ECO mode when 'ocm' symbols exist in the SiP file
2301724 When separate history management is enabled, Virtuoso exits unexpectedly after copying a maestro view and deleting a history point
2301209 Enable the traceTxChainWithDirComp flag in vpmSetEnvVals()
2301206 Enable the extendedHierCellTermDirCheck flag in vpmSetEnvVals()
2301072 Parametric sweep fails with ERROR (ASSEMBLER-2343) using dependent variables
2300228 Parameter not set in the netlist when using calcVal and variable sweep in the corners
2299793 Handle automatically created RPP for single rail level shifter cells in Virtuoso Power Manager
2299786 Handle three-terminal devices in supply and data path in Virtuoso Power Manager extractor
2299778 Virtuoso Power Manager extractor to support three-terminal capacitor devices
2299767 Virtuoso Power Manager setup to support registration of three-terminal devices in the capacitor category
2299373 Virtuoso Power Manager missing pg_pin definition in the exported Liberty file
2299234 Virtuoso stops responding when using recursive variable in ADE Explorer
2299076 Virtuoso exits unexpectedly when non-static data members of a class are not initialized
2299013 Operating Region Violations option missing in the context menu of the Detail results view
2298616 Noise summary feature does not work as expected on specifying instances through the 'Include Instances' field
2298606 The Spectrum assistant rounds off stop time, giving wrong THD results and spectrum plot
2298548 FastC Coupled C becomes smaller when side metal is in a specific range
2298313 XOasis Out does not set strict flag for layerNames in OASIS files
2298035 Can we run Modelwriter in IC6.1.8 ISR12?
2297815 The clip function does not work with a family of voltage waveforms in the Monte Carlo simulation
2297684 Unable to launch Verify Design UI
2297489 Unable to resize a graph strip in Virtuoso Visualization and Analysis XL
2296131 Virtuoso Power Manager extracting incorrect pg_function for a few pins
2296127 Virtuoso Power Manager missing pg_function for a few pins
2296004 Virtuoso Power Manager extracting incomplete pg_function
2295351 Virtuoso exits unexpectedly when specifying the setup data in Data View assistant
2294844 Slow performance when leHiFlatten command is run
2294441 The Auto Via command is choosing larger enclosure than expected for GM0 metal
2294333 pz analysis results are plotted in wrong axes
2294162 Filter issues for multiple corner model setup in Detail-Transpose results view
2293292 Virtuoso Power Manager is inheriting VDD/supply attribute from cells in the ignore category
2293289 Virtuoso Power Manager extractor does not contain pg_function values for few pins in scratch mode
2293284 Update the Noise Summary form in IC6.1.8 ISR7 to support wildcards when selecting instances with hierarchy in the schematic
2293277 Size Over Corners fails unless OK is clicked on the new Size Over Corners options form
2293273 Size Over Corners does not proceed with corner analysis
2292266 When editing virtual hierarchy, switch back to the workspace that customer used to work in Layout XL
2292256 Display all local nets up to the virtual pins within a virtual hierarchy when doing Select - Local Nets on a selected virtual hierarchy
2291881 Options on the Harmonic Balance Noise Analysis form do not display correctly when Noise Figure is selected
2291692 SKILL function ddsSetLibManLCV does not work on combined libraries
2291057 While accessing Self-Heating Effect analysis reports, on reverting back to text files from html files, the text files go missing
2290993 Checker exits unexpectedly if a layerIndex value for a layer specified with minVoltageExtension is 0
2290870 Virtuoso exits unexpectedly when attaching a technology database to a library
2290004 AMS UNL netlisting assembly does not work as expected in IC6.1.8 ISR10
2289577 Add model name to the exported Unified Power Format file
2289480 Performance is degraded during interactive edit operation for DI associated object
2288933 ADE Explorer allows adding temp in design variable
2288846 Virtuoso stops responding when using multiple tabs
2288273 ESD Optimizer removes vias that should be retained in the optimized DSPF file
2288267 The ESD HBM waveform shows an incorrect current value at t=0 that does not match the schematic value
2287209 ADE Verifier ignores the values in the Verification Space column when importing data from a CSV file
2286809 Unable to change order of the pin in Pin Tool after "Create Pin Template" utility is invoked.
2286617 Add the argument rcr=selected to the Solver Method table on selecting Iterated as the solver method
2286597 Pin Optimizer fails when there is a mosaic in the design
2286453 Links with literal equal sign (=) do not work with the hiCreateHypertextField
2286247 Virtuoso exits unexpectedly when pasting objects that include one or more traces
2285890 Layout XL stops responding when using Gnome window manager
2284658 Provide the support to register any instance as header or footer type special cell
2284010 Additional argument 'Exclude' for net analysis in the ADE EMIR Setup form gets appended as a new line in the Summary Information table
2283915 Pre-simulation of an operating region spec is stopped when ADE Assembler uses a local host
2283485 DRD does not report minExtensionEdge constraint violations
2283273 A strange stdVia remains when we escape the command during wiring
2283202 Virtuoso Power Manager not extracting the expected isolation strategy signal
2283171 Additional internal power pins found for related power pins
2280242 Performance degradation observed when transitioning from ADE L to ADE Explorer
2279815 When working with the Make Cell operation, selected objects are losing connectivity
2279021 Virtuoso Space-based Router introduces maxWidth and allowedWidthRanges violations when hitting offGrid pins
2277658 Unable to create a via using the Auto Via command due to shape on cut layer though purpose of cut shape is specified in viaIgnorePurposes
2277395 The autoSave environment variable does not work in IC6.1.8 and ICADVM18.1 ISR9 or later releases
2277352 Found libImport errors in Allegro board file
2276459 DEFOUT of path objects adds unwanted horizontal extension at 45-degree transitions
2276436 Library copy must also update target and footprint library name parameters
2276425 Provide support for package footprint export of an imported SiP layout
2275830 The awvSetLegendWidth function does not work with circular graphs
2274889 Remove the Set Valid Layers form
2273262 Memory consumption increases when using noiseSummary() statement in the OCEAN script
2273154 AMS UNL netlister with arrayed instances in the SystemVerilog code causes an EXNEUS elaboration error.
2272602 Additional internal supplies in exported Liberty file
2272601 Virtuoso Power Manager missing pg_function for a few pins
2272060 Virtuoso exits unexpectedly due to segmentation fault in axlPlotSingleOutput
2271313 Virtuoso exits unexpectedly when pasting objects that include one or more traces
2270877 Runams adds -flow argument to the probe.tcl file on restarting, which causes Spectre to fail
2270654 Update Components and Nets should replace existing pin in case Design Intent for that pin is updated to different layer or width
2269647 Support for module type in the Co-Design flow
2268969 Co-Design does not work if the fabric type is module
2264905 Extracting VerilogAMS cellviews stopped working since IC6.1.8 ISR6
2264534 Yield view shows incorrect results when using the VAR expression to define specifications
2263432 Line chop in minSpacing mode chops pathSeg placed outside prBoundary with larger value than required
2263427 Line chop in minSpacing mode does not chop rectangle placed outside prBoundary
2262620 Implicit signals are not generated because of a specific sequence of changing 'Save all' options
2262063 Spectre assert statements return 'inf' for Duration (%) in ADE Assembler output Checks/Asserts table
2259594 Virtuoso exits unexpectedly when running an EM simulation using a smart view
2259565 Smart view is not netlisted correctly; shows a warning that the view is not a valid extracted view
2259521 Layout XL: Incorrect extraction for a MIM capacitor in two-metal stack configuration
2258187 Double-clicking a signal waveform incorrectly works as the Plot All command
2255264 The 'filter_ir_percent' option does not work in Voltus-Fi
2254523 Update the *WARNING* (LCE-2045) message to reflect the actual type of the layer instead of using the term 'logical layer'
2253741 Setting the environment variable groupRunA to nil causes identical corner point runs to be linked and not rerun
2252419 The footprint Library Name property does not automatically update in Schematic Edit Object Properties
2246655 Performance issues when waiving more than 10k violations
2246026 Measurement across corners is not working correctly for expressions without name
2245814 ADE Explorer slower than ADE L when ignoreDesignChangesDuringRun is set
2244573 Virtuoso RF Solution: Instantiated pins are no longer visible after changing the name of the Export Die library
2243791 Allegro Import translation fails with SiPtoOA error
2237464 Virtuoso exits unexpectedly when pasting objects which include one or more traces
2237124 IgnoreDesignChangesDuringRun breaks netlisting if only Parameters check box is enabled
2236937 Virtuoso exits unexpectedly when using the Fit Visible Traces command
2235874 Modgen template reuse gives warning and fails
2235872 Virtuoso exits unexpectedly when running simulations in ADE Assembler
2232020 Virtuoso RF Solution viaSelectionMode use non-Cutlayers blocks via selection
2229395 Limiting voltage parameter in variableGainAmplifier in Functional Library does not work
2228879 Output expressions with plot and save disabled should not be evaluated
2222659 Discrepancy between spectre_ddmrpt and ADE assembler fault report
2222582 Appearance of statement aging_analysis_name value=dc in the netlist
2215721 Renaming an unmanaged library overwrites the DMTYPE setting in cdsinfo.tag
2213922 Router routes over blockages for some differential pair nets
2210847 Renaming an unmanaged library overwrites the DMTYPE setting in cdsinfo.tag
2208481 Model group name containing a dot (.) causes an error in worst case corners
2204742 Virtuoso exits unexpectedly when the hiRegZoomPanProc SKILL function is used
2203332 Spectre reliability relx_tran argument truncates decimal points
2200925 Reference History does not work as expected when using variables dependent on each other
2190802 Checks/Asserts tab reports 'inf' for Duration (%)
2188074 The rodFillBBoxWithRects SKILL function is creating fill shapes outside the given bounding box
2182019 In Pin to Trunk routing, Trunk Extend extends the trunk outside of selected area
2170762 ADE Assembler consumes large amounts of memory and does not release it until Virtuoso is closed
2150446 Pin Placement is creating shorts for existing power pins
2147838 SKILL function ddsSetLibManLCV does not work on combined libraries
2141130 Release memory after ADE Assembler is closed
2128122 The leGetCoordinateForm (bindkey Shift+N) Pan-to-coordinate is not compatible with infix mode
2112949 Discrepancies in the results displayed in Detail view and Yield view
2110671 Bug in waveform comparison across corner
2098875 Memory no longer needed by ADE Assembler should be released to OS
2067163 Memory consumed by ADE Assembler is not released when the tool is closed; need to close Virtuoso
2064375 Incremental netlisting does not work with AMS Designer in ADE Explorer
2035506 Typical implementation does not work with the model files that do not have section details
2025368 Incremental netlisting does not work with AMS Designer in ADE Explorer
2020300 Pin To Trunk routing chooses offset via for simple pattern
2007678 In ADE Assembler, the Create Test Copy command in the context menu of Corners does not copy enabled corners in the Corner Setup form
1994369 Creating a Test Copy does not copy the corners setup
1961784 Specifying a variable in the Relative Harmonic field in the Periodic Noise Analysis setup gives an error
1954211 IgnoreDesignChangesDuringRun breaks netlisting if only Parameters check box is enabled
1928931 IgnoreDesignChangesDuringRun breaks netlisting if only Parameters check box is enabled
1832041 SKILL function ddsSetLibManLCV does not work on combined libraries
1767782 Allow to waive corner-specific violations
918684 Renaming an unmanaged library overwrites the DMTYPE setting in cdsinfo.tag

October 2020

2551574 Tcl files already specified in the setup are not being passed to xrun in ICADVM20.1 ISR19
2549449 Virtuoso exits unexpectedly with assertion failure in ABE
2548865 oaScan fails if cds.lib is not located in current working directory during the Design Integrity check in Performance Diagnosis
2548826 A Monte Carlo run ignores the config sweep settings in ICRP job control mode
2548061 Config sweeps do not get netlisted again when the variables simReNetlistAll and nlReNetlistAll are set to nil in the .simrc file
2547445 Stacked config sweep picking up wrong cellview
2545788 Incorrect status of jobs is shown in Run Summary when using LSCS
2545179 DRD check clean not returning violation markers for maxViaArrayClusterSize with maxFacingEdgeNeighbors
2544389 Virtuoso exits unexpectedly when the Mark Net command is used
2543251 Virtuoso exits unexpectedly on routing a net in a customer testcase
2542488 Allegro Import translator fails when used with 'Generate Instances as in Schematic'
2542305 Pin order mismatch between instance and subckt in ICRP netlist
2541686 Allegro Import translator fails with 'strcat' error
2541425 Mismatch in number of VSync shapes created in ICADVM20.1 ISR19 and ICADVM20.1.ISR20
2541012 Concurrent Layout exits unexpectedly when editing in a design partition with internal errors
2540781 Allow terminal voltage probing when preserveSubcktTermNamesByOrder is set to t
2540117 Allegro Import fails when used with 'Generate instance as in Schematic' to make a design Virtuoso RF compatible
2539323 Virtuoso exits unexpectedly with error mapiMngr::deleteSession
2539172 Idle jobs block launching of next simulation
2539079 Virtuoso Power Manager to improve the exported expression by removing additional or unwanted elements and objects
2538201 Virtuoso Power Manager: Add support for identifying name-based Charge Device Model cells
2538082 Virtuoso Power Manager exits unexpectedly for a design
2537865 Some netlists are not correctly linked to .tmpADEDir; thereby causing simulation issues and showing menu of ICRP in LSCS
2537561 After making a change in the HED, running an AMS simulation in ADE Explorer results in a UNL netlist error
2536729 mptColorRemastering() command does not work in Virtuoso nograph mode
2536560 Wires accidentally deleted during check&save
2535540 Unable to run the Pin to Trunk command in ICADVM20.1 ISR18
2535436 During Allegro Import translation slivers of dynamic shapes are left behind creating false shorts
2535380 Userdv shape is not created on top level shapes.
2534450 Virtuoso stops responding while running ocnPrintTMIReliabilityResults()
2533235 auCDL does not netlist properly in IC6.1.8 ISR19
2533197 Error in phoWayPointConnector due to undefined variables
2533094 Reliability Report: In case of large netlists, ADE Assembler stop responding after age simulation has completed
2531906 Virtuoso Power Manager: User-defined macro flow missing switch pin and switched power in the exported Liberty file
2531902 Virtuoso Power Manager: User-defined macro flow changes for the switch pin attribute
2531875 Distributed netlist jobs linger for 300 seconds due to Start Timeout
2531761 In Concurrent Layout a synchronous copy in a design partition conflicts with same name object in other design partition
2531255 Remove inversion from the pg_function for virtual ground pg pins
2531227 Change in voltage map after user-defined macro registration
2531222 Switch pin attribute missing after user-defined macro registration
2531219 Switch function missing after user-defined macro registration for one of the pins
2531218 Switch cell type missing after user-defined macro registration
2531001 Incorrect netlist generation on running a device parameter sweep with a config sweep
2530920 Stretch command is leaving behind associated vias when KeepWiresConnectedToShape mode is selected
2530828 Sanity Checker, label vs dataset, is not checking worst case dataset value based on all the dataset selection
2529940 CDLOUT produces netlist with instance parameter missing from the diode defining statement
2529461 Virtuoso exits unexpectedly in tpaSetActivePattern()
2529330 Virtuoso exits unexpectedly when 'Update Components and Nets' is run in Virtuoso Layout Suite XL to update the pins
2529159 The auto twig functionality in simulation-driven interactive routing places vias but fails to connect some of the cells
2529141 Extremely slow copy of test through the Create Test Copy command
2529117 After migration to ICADVM20.1 ISR19, Tcl files already specified in the setup are ignored by the simulator
2527883 Virtuoso RF Solution needs a Read-in-Concert functionality
2527643 Idle netlister jobs will start shell process to touch a file
2527598 When using LSCS for a run plan, some points need to wait for a long time for job assignment
2527376 Icons in collapsed toolbars not working
2527189 cstGetFoundryConstraintGroup error displays a warning message for fluid guard ring during Quantus extraction run
2526977 isInterface check for bus terminals is not working properly
2526456 When S-Parameter analysis is used, Direct Plot adds a white space after the expression name in the outputs
2526371 Digital signals cannot be plotted during an ongoing AMS simulation
2526345 In-design checks: Sub-hierarchical in-design checks run uses high memory consumption
2526343 In-design checks feature printing repeated warning messages in the log file
2526341 In-design checks run on sub-cell taking too long to run
2526097 The Mark Net command has incorrect highlight result
2525730 Virtuoso exits unexpectedly when Edit – Hierarchy – Check command is run, and value of reference library is long
2525629 Virtuoso Power Manager is not tracing pg function for internal powers
2525616 Virtuoso Power Manager is consuming high memory for designs
2525563 The 'Enable Encryption' option in the Virtuoso AMS IP Export Reuse flow encrypts only the top-level netlist
2525394 Run Preview does not honor point selection
2525172 EM assistant Preview EM model is not working for Clarity model setting
2525100 Batch extractions needs to be run two times to locate the shorts
2525089 Virtuoso Power Manager printed backtick character as hierarchy separator in a few cases in the exported Liberty file
2524729 Virtuoso exits unexpectedly while evaluating a point
2524714 Spectre monitor gets stuck with the MPS error message
2524069 Distributed job launched on SGE remains in pending status
2523787 Failed to map schematic to smart view stitching errors for an LVS clean layout
2523651 xFGR Support for Metal and contact minOppExtension
2523485 Make sure the design netlist is reused for the runs in the run plan
2523482 Make sure design netlists are reused on tests with the same design even when calcVal is used
2523397 Running an AMS simulation without the MTS settings results in an error
2523179 Cannot use application name 'Layout XL' when leGetAllApplicationNames is used with deGetLowerTierApp
2523034 Netlisting service gets stuck when receiving an invalid message
2522992 An error message is displayed on running Wireless Analysis
2522441 Extracting objects only on the top hierarchy (Hierarchy Levels = 0) does not work as expected
2522347 In ICADVM20.1 ISR19, Virtuoso Space-based Router leaves some opens while bus routing
2522187 DesignSync design management environment for die export does not check out all the necessary view or files
2522150 leReportTrimmedShapesInCustomStyle does not report violations for missing pathSegs abutting trim shapes in same cellview
2521943 GFS virtual hierarchy area boundary generated by utilization percentage for all levels creates device overlaps
2521819 Make sure the design netlist is reused if the same DUT is used for the runs in a run plan
2521798 Spectre monitor cache problem is leading to a long evaluation time
2521786 Ensure that LSCS follows ignoreDesignChangesDuringRun strictly, even for run plan and other cases
2521784 Virtuoso exits unexpectedly for a run plan testcase before netlisting jobs get started
2521671 Virtuoso exits unexpectedly when trying to connect to beanstalk
2521668 Preview options are modified when the preview state is checked
2520471 Optimize point netlisting time
2519965 Virtuoso RF Solution-EMX: Preview EM Layout Issue
2519886 Property Editor fails to modify properties when multiple objects are selected
2519616 ?getFirstSweepPoint does not work for local sweeps with multiple calcVal dependencies
2519205 Digital signals cannot be plotted during an ongoing AMS simulation
2519093 For vmtLibImport, library check in/out should also perform check in/out for all the available files
2518941 The ICRP job control mode does not work with the new history management system in ADE Assembler
2518865 In ICADVM20.1, Virtuoso Space-based Router routes partially
2518813 Provide correct setup prompt when single simulation SHE flow is enabled or disabled
2518298 When running slotbyNet, sltShapeConsecutiveSlotting slots vias which do not belong to list of objects to be slotted
2517879 leLayerAndNot gives different result in IC6.1.8 ISR11 and IC6.1.8 ISR18
2517740 vmtLibImport needs to handle and update part.csv under design management environment properly
2517077 Retain the manual setting +postlpreset=OFF in the GUI when switching between presets
2516787 Point netlisting takes very long time in the DSPF flow
2516371 In hiCreateToggleField, enabledItems is not in sync with enabled attribute
2514702 Delete AGR and Fill option is not displayed in the context menu for merged AGRs
2514129 During concurrent layout editing path segment becomes longer after split if its end segment is outside design partition
2514111 Virtuoso exits unexpectedly: vvSetCurrentWindow after ddtUpdateGraph
2513933 Placement of instances is scattered when virtual hierarchy area boundary is stretched
2513420 If one side of an object is less than or equal to partition area halo, then this side of the object is not split
2513416 Temperature color map at stop time of transient is not displayed
2513400 In a design partition with multiple area boundaries 'Split Object Crossing Partitions' works only for one of them
2513280 LVS fails when the diffstbprobe component is removed from the netlist but not shorted like a voltage source
2513057 The SystemVerilog Netlister creates a netlist with multiple wire declarations resulting in compilation errors
2512989 Double RMB click bindkey for context menu does not work
2512819 Quantus transfer property functionality is missing multi-cell placed device properties
2512655 Netlister is not netlisting VAR expression correctly for some of the points
2512646 Point netlisting takes very long time when the DSPF flow is used
2511466 Digital signals cannot be plotted during an ongoing AMS simulation
2511462 Running an AMS simulation with a single SystemVerilog block gives an *E,WKLNDF error during netlisting
2511239 Bumps alignment check fails after bumps are propagated
2511164 Virtuoso stops responding during Discard Edits when edits are done across multiple tabs
2510116 Virtuoso exits unexpectedly when axlShowHideOutputSetupNamedFilterItems is run
2509633 Error if signal is plotted from HB analysis
2509607 AMS UNL flow gives an error on changing the config view; error points to the Pcell variant
2509111 ADE XL to maestro conversion causing AMS elaboration error for iterated instance varactors
2509013 Virtuoso exits unexpectedly when running EM analysis on a setup using qrcTechFile and emDataFile
2508640 Digital signals cannot be plotted when running simulations from ADE Assembler
2507631 After running an AMS simulation in ADE Assembler, viewing the netlist results in the readTable error
2507458 Virtuoso becomes unresponsive when using the 'Auto adjust area boundary' option with width and utilization
2506956 Error ADE 5019 is reported when trying to disable hysteresis DC analysis in Multi-Test Editor
2506943 Logical trace net bypasses trim layers
2506474 Virtuoso toolbars with extend button do not work properly when using the XFCE desktop
2506416 AMS fault simulation does not work with config DUT
2505856 Virtuoso toolbars with extend button do not work properly when using the XFCE desktop
2503270 Performance diagnosis for library shows 'ldap' server path. Need clarification on what it means
2503215 Layout editing on package level is slow even when extractVerifyInvalidConnections set to nil
2502219 sigType of existing nets and pins change when the sigType of a new net is changed
2502216 A tiny step is generated when a path object split during concurrent layout editing is stretched
2500960 Virtuoso RF: Simulation stops with an incorrect error when mixed sampling type is used for an EMX model
2500494 Results merge with run point selection does not work correctly when clicking the blue run button
2499019 Physical point at which the second event triggers is altered by shapes not related to abutment
2498627 allowedSpacingRanges is not flagging some violations with tapered widths
2497438 Allow the user to set their own EMX settings in UI
2496830 Virtuoso Power Manager does not extract Antennae Diode Related Power Pin for dummy and is always off for devices
2495332 The Compare & Merge flow does not detect deleted rows from a CSV or Microsoft Excel file
2494577 Two area boundaries are generated when pressing Enter key to finish specifying the partition area
2493583 define_signal_attributes do not handle power sniffer circuits having tx gate controls with feedback loop
2493564 Virtuoso Power Manager user-defined macro testing: Switch function and related ground pin change
2492636 DRD check clean is not returning violation markers for maxViaArrayClusterSize with maxFacingEdgeNeighbors
2491689 Display a warning when odd multiple width in a netClass would cause Virtuoso Space-based Router to route offGrid
2491665 Results view shows incorrect values while scrolling
2491480 The Reference Histories form in ADE Assembler does not allow selection of pending simulations
2491054 The 'DC Operating Points' option is greyed out on using Schematic Annotation in Virtuoso
2490528 hiCloseWindow segmentation faults in processOpenCVHasOAException
2488358 Improve via alignment when a minQuadrupleExtension constraint generates an asymmetric via not contained in the overlap
2487607 Running an AMS simulation with a single SystemVerliog block gives an *E,WKLNDF error during netlisting
2485447 Pin net collision after pin name change with new extractor
2483407 axlSetHistoryPrefixInPreRunTrigger allows invalid history names
2483353 Setting the temperature value in the Setting Temperature form clears the temperature specified in the Corners Setup form
2481278 Cannot deselect a trace family by clicking in the background
2481275 Cannot toggle the trace visibility for a trace family by using the context menu
2480612 Search in Data View is slow as it searches all the setup states
2476342 Descend edit for config view does not open schematic view
2467268 Run status shows pending and shows the 'Error while configuring the job' message in job log
2465667 Virtuoso exits unexpectedly due to segmentation fault in hiRaiseWindow
2459654 Signals are not plotted in the Results Browser when running an AMS simulation
2453440 Results view shows incorrect values while scrolling
2450149 In ADE Assembler, results filtering is canceled after interactive toggling of tabs in the Results view
2443148 Export Die will export matching the instance terminal and not the pins on the instance
2442967 Virtuoso stops responding when opening waveforms in Virtuoso Visualization and Analysis XL
2441236 Buttons get removed from the Models column when Reset is clicked after filtering in MTS Options form
2441227 In MTS Options form, clicking Update after adding filters for Library and Cell adds extra rows and extra buttons
2439330 Pin error when generating em_solver extracted view because of schSnapSpacing
2436453 ADE Assembler stops responding for a long time after the column width is auto adjusted if the Results table is bigger than the window size
2435642 Allow canceling of the ADE Assembler Save Setup question that is shown when exiting Virtuoso
2428192 Get 'Ineffective Global Job Policy' pop-up when changing job policy for a maestro view with no tests defined
2427600 Add a placement lock to figGroups
2422944 Calculator gives incorrect results after evaluating the expressions in the Buffer
2420690 hiSetCurrentWinNum segmentation faults
2412237 Properties of ROD multipart path objects not edited as expected when using SKILL
2399151 Virtuoso exits unexpectedly when modifying a multipart path
2399138 Global Signals form does not save changes to existing settings
2295871 All forms are pulled to the foreground when Edit Properties form is invoked in RHEL6 in IC6.1.8 ISR11 and ISR12
2295279 After AMS simulation, plotting a current signal directly from ADE XL shows the WIA-1006 error in CIW
2272466 During fill insertion, add an option to fill neighboring OD shapes belonging to the same row
2255542 Issues in the 'Select Tests are Displayed in Table' list on the Results tab after using the Plot Signal command
2253084 After a post-layout simulation with a DSPF file, unable to plot current data from ADE Assembler, but can plot the same from Results Browser
2249702 Allow signal type check between symbol pin and corresponding schematic pin on same cell
2246134 SKILL function awvPlotExpression gives error for AMS simulations in IC6.1.8; worked fine before
2241695 The 'Select which tests are displayed in table' filter shows all the listed tests as checked even if simulation is not run for all tests
2224397 When the -env ade runSimulation option is used in IC6.1.8, the current expression is different from the one that was added in IC6.1.7
2222105 After running a Spectre APS Monte Carlo simulation with a DSPF cellview, eval error is shown for an IT expression with a node current
2215367 Allow cross-view checker to check for signal type
2214529 Icons in collapsed toolbars are not working
2178982 For external text views, terminal current cannot be saved or plotted due to the '-env ade' argument
2062154 EAD cannot extract a resistance when 'Extraction Mode' is set to 'RC coupled'
2026432 Incorrect well merging because wells are hardcoded to connected 'B' terminals
2014147 Need a cross-view check for sigType property
1994353 Virtuoso stops responding when opening waveforms in Virtuoso Visualization and Analysis XL
1825696 Make sure the design netlist is reused if the same DUT is used for all runs in a run plan
1700431 In ADE Assembler, results filtering is canceled after interactive toggling of tabs in the Results view
1441002 Enhance Cross-View Checker in Layout L to prompt sigType mismatches across views
1147114 Add capability in Cross-View Check to check mismatch of signal type
862348 Check must enforce the same sigType values on pins of the schematic cross views

October 2021

2574047 The mouse cursor for Virtuoso changes for the session after running a simulation with run plan
2573614 Add another parasitic diode flag with the default value as t
2573456 Via stack creation fails on overlaps in Auto mode and creates lower vias with only one cut in Stack mode
2573297 Netlist creation for a Smart View returns (PARA-3001) error
2571553 Unable to run the background in-design checks if the main Virtuoso session is started using the -cdslib option and cds.lib does not exist in the current working directory
2571537 Do not print cellview IDs that have been purged in the background in-design checks run log
2570257 Waveform for real number is not plotted correctly in Virtuoso Visualization and Analysis XL
2570251 The Placement Planning form in Virtuoso Layout Suite takes a long time to load in ICADVM20.1 ISR21
2569223 axlSetHistoryPrefixInPreRunTrigger no longer accepts empty string for the prefix name
2569161 Netlisting errors for all newly run points when using reference history
2567926 Sanity Checker reports VDR voltage label on lower hierarchy instances mismatch with different vdrSharedCellList
2567253 Virtuoso stops responding when a cellview is opened in Virtuoso Layout Suite in ICADVM20.1 ISR21
2566842 Virtuoso exits unexpectedly due to axlDataViewSelect and axlDataViewSetDataInt
2566052 Virtuoso exits unexpectedly when ADE Assembler window is closed after a simulation is run but netlisting jobs are active
2565446 Virtuoso exits unexpectedly when the Hide Overridden Variables' open is selected and a local variable is unchecked
2565142 Clicking SDP-Export Die does not work in IC6.1.8 when using the virtuoso -sdp command to launch Virtuoso
2564973 Calculating the Noise Figure (NF) through a new server gives wrong results
2564935 Problem when using NF from the direct plot in conjunction with the 'Magnitude' modifier
2562785 Number of protected level shifters reported does not match the real number of level shifters
2562784 Unable to run in-design checks due to a SKILL error
2562475 Xcelium 21.09-s009 does not work with Virtuoso IC6.1.8 ISR21
2562233 Wrong via created for area-based allowedCutClass constraints
2562217 Make sure the DM status title bar for a maestro cellview is correctly turned off if DM information is incomplete
2562189 Provide an option to hide the Run command in the context-sensitive menu of a run in the Run Plan
2561859 The Create Via form ignores the definitions defined by cutClasses
2561338 REGRESSION: The dB10 option in the Direct Plot/Main form for NF calculation does not work as expected in SP analysis
2561220 The latest Xcelium release version is incompatible with the latest Virtuoso release version
2559511 auCdl Netlister in foreground mode resets ael significant digits to default after completing the netlisting
2559348 Starting from IC6.1.8 ISR18, the custom function template file cannot be loaded in Virtuoso Visualization and Analysis XL
2558875 VSR seeds obstructed routing rather than connecting to clePin on partition boundary
2558588 Sanity checker to check and print mismatched VDR label value for Vmin/Vmax based on user-set precision value
2558423 ADE generates inconsistent save statement across corner simulation
2557987 Netlisting fails when idle netlister jobs are used, but works fine when netlisters are restarted
2557837 1.2x increase in VM consumption while executing Auto Via
2557087 Quick Align (leHiQuickAlign) does not give expected results when drawing shapes overlapping metal layers with MPT purpose
2556637 Legato: Virtuoso stops responding when the run mode is changed from 'Fault Simulation' to 'Single Run, sweep and corner’
2556464 Variable values are not evaluated correctly
2556298 Case-insensitive sorting of terminals causes failure in CDL netlist generation with partial CDF when auCdlCDFPinCntrl is set to t
2556207 AMS simulation gets stuck at the netlisting stage
2555920 Random behavior in calcVal including nil return values and calcVal expression in netlist
2555830 Display the preview alignment ball when Fill Polygonal Overlap is set to Partially in Auto via mode
2555734 Results of fault dropping using a run plan cannot be merged by the Merge Fault History command
2555598 Virtuoso Power Manager: Incorrect optimization of the isolation_enable_condition and switch_function commands in some cases
2555035 Netlist creation for a point gets stuck waiting for an exclusive lock
2555031 Full netlist is copied into the point netlist directory before it is replaced by a link
2554981 Checker misses flagging eolKeepOut with jointAsEol parameter
2554934 AC noise summary shows huge noise contributions in Spectre 20.1
2554824 openResults takes time in ICADVM20.1 ISR20
2554777 Supply net and port extraction takes more than three days while running in-design checks
2554526 Virtuoso Power Manager: Empty switch function is printed with only the opening bracket for a specific user-defined macro
2554464 Virtuoso Power Manager exits unexpectedly when automatic identification of logic devices in back tracing paths is done
2553880 Create Fill and AGR command makes Analog Guard Rings with different analog cell types
2553222 Simulation with Run Plan reports a 'Cannot find a setup database entry for handle 0' error
2552738 Virtuoso Power Manager function 0/1 pins are not handled correctly in the user-defined macro flow
2552491 Auto via creation fails due to the minEndOfLineEdgeExtension rule
2551648 Simulation failed because of an extra closed bracket
2551599 Point netlist is completely wrong for one specific corner and some tests
2550902 maeDMAddDMStatusToTitle error happening in custom SKILL
2550866 Netlist error when config sweep variables are not defined in the Global Variables list but are used in corners
2550865 The foreground and background order of traces changes when saving images
2550778 The AMS Designer interface causes netlisting error when a Spectre simulation is run
2550616 ICADVM20.1 ISR20: The report_shield_wires command does not report shielding for trunks and issues an empty report
2550170 Virtuoso exits unexpectedly when using the info statement with oppoint=all
2550138 CLE: Prompts for each hierarchical design partition view after Merge even when opted for no prompts at Auto Checkout
2550096 LSCS is creating design netlists for all config sweep combinations between different corners
2549977 auCdl netlisting not as expected when partial terminal information is given to CDF and hnlProcessDifferentPmAndInstTerminalRepresentation is enabled
2548807 Exporting waveforms does not work when the 'Use names from graph' check box is selected
2548743 spfFileHierDelimiter causes an incorrect save statement
2548551 In ICADVM20.1 ISR20, Virtuoso Space-based Router is unable to route inside figGroup
2548456 Existing design intent constraint members are repeatedly added to design intent list during Check & Save
2547904 Test named 'sequence' causing incomprehensible error message
2547103 Incorrect Virtuoso System Design Platform header with a mismatch in layout net name versus port mapping leads to failure in creating an extracted view
2545905 Trim insertion should create only DRC-free cut shapes and skip shapes that would create DRC spacing/other errors
2545903 Wire Editor is unable to support one-side-aligned via
2545843 Line wrap in IC statement causes xrun to fail
2545576 Running the Promote Pin command adds instance name prefixes
2545388 Pin to Trunk generates inconsistent results on different WSP patterns
2545190 Virtuoso Electromagnetic flow to set BottomIncludeSolderMask or TopIncludeSolderMask for package instances in .rficpost
2545147 Virtuoso Electromagnetic flow to give warning and continue exporting a .clf file when sball/sbump height is less than solder mask layer thickness
2545069 Incorrect design intent layout sync status after syncing, saving, and reopening layout
2545062 Design intent net annotation shapes are not following wide wire reference shapes
2544302 The drag-and-drop feature in Pin Tool does not optimize pins correctly
2544083 ICADVM20.1 ISR20: Mesh router cannot insert VIA0 between M0 and M1 when there is a CM0 layer
2543393 Virtuoso exits unexpectedly with the JobAcquiredNewTokenException exception
2543091 Dynamic display of extraction results does not work when the drawn layer is a derived layer
2542917 Virtuoso exits unexpectedly during CPH updates
2542727 Unable to override prefix using netdpl
2542276 Virtuoso exits unexpectedly in checks/asserts run
2542261 Virtuoso exits unexpectedly when running ADE Assembler or ADE Explorer
2542193 Issues with the Stress File Configure option for reliability setup
2541416 Simulations that were running successfully in IC6.1.8 ISR15 return sim err in IC6.1.8 ISR18
2541356 A ghost image appears in some advanced node environments
2540978 Undefined function 'umberp' in phoAutoWide
2539867 Retain MTS settings during design changes
2539689 After running the Direct Plot command, adding outputs from the schematic of bus nets in the hierarchy uses incorrect bit indices in the expression
2539443 Virtuoso exits unexpectedly when initializing EAD
2539163 Create a check for the problem with netlists wrongly linked to tmpADEDir
2539160 Changing the Voltage property of a virtual connected net does not update all labels
2539001 Orientation information is not generated correctly in ADA
2538992 Some Modgens generated in the APR Flow are not abutted
2538909 Cellview in the open Extract Layout form not consistent with the cellview in the Connectivity form
2537431 Omit the Mean column from the user-defined statistical variation CSV export
2537374 Stretch of virtual clones in constant area mode is not working at level -1
2536399 While editing a bus, the control wire keeps the original highlight (wire width) size
2536091 Unable to view results after running the Move to Read Only History command in the context-sensitive menu of a history
2536075 libInit.il from all libraries getting loaded when attaching a design library with a technology library
2535492 Notification to user when nested config sweep is used in context of configs sweeps
2534642 Clicking Module-Create-Bond Wire results in wrong wire diameter
2533191 Running Pin to Trunk gives poor quality of result unless a shell environment variable is set
2533117 The mapping of DSPF device names in expression OT() is incorrect
2532874 autoAbutment moves the wrong instance
2531217 Change in coupled supplies after user-defined macro registration
2531203 Related power pin and PDF change for one of the designs after the user-defined macro registration
2530983 pg_function changes for one of the designs
2530783 Tool is unable to notify the violations for cell level shapes
2530049 Virtuoso Power Manager: Bug in a user-defined macro run versus a non-user-defined macro run for isolation_sink_ground_pin
2529892 Incorrect prefix in the netlist for Smart Views when a 3rd-party simulator is used
2526534 Mask color not displayed when descending from Schematic to Layout view
2526447 User probe trigger not called when a probe is removed from schematic by using context menu in Navigator
2525445 Inconsistent mouse pointer used in run plan simulations
2524867 Stress configure: If the history name changes for stress run, tool tries to grab config for age run with the updated history name
2524101 Strange mouse pointer when run plans are used
2523980 Enable area and point selection of empty text when using geSelectArea
2519426 Failed to open Library Compilation Form through the AMS Options form
2518240 Snap to grid for symbol views incorrectly moves pins based on vertex rather than center
2517571 abeLayerInside returns partially overlapping shapes
2516922 Virtuoso stops responding when updating HighCurrent design intent
2515122 Patterns with iterated instances not synchronized between GPE assistant and the Text tab of the ADA assistant, and the Apply button does not function as expected
2514913 Provide a function to remove a configuration ID from a window without using deOpen
2512617 File compare and merge flow does not add a new entry if the ID has changed
2511869 *ERROR* (AMS-1351): There is no valid DPL file when SystemVerilog view has file included with relative path
2510716 Using rfOutputNoise from the result of a batch run causes errors
2510363 Unexpected behavior of global variables and local variables in ADE Assembler
2509978 Add ocean script writes into the cellview even if it is opened in a read-only session
2509041 Transient option skipdc provides only 6 of 8 possible options
2507332 Dependent variables do not get properly evaluated across corners without VAR function
2504912 Virtuoso Visualization and Analysis XL: How to annotate a swapSweep with 'corner' as a sweep variable
2503380 Add decompCnt to the beginning of the fingercount parameter list because the Auto P&R assistant is not adjusting the Modgen correctly during placement
2503212 System slows down during cleanup of invalid connections
2500307 Add the error and cancelation information in the new HTML report
2497697 Issues with CLF export to Clarity when IC is mirrored
2490146 IC6.1.8 opens all PDK libraries and invokes its libInit.il when creating a new library
2489765 The Auto Device Array assistant should show the dummy width parameter names properly for mature node technologies
2487492 The AMS PBSR flow gives a netlisting error in ADE Explorer
2487004 ICADVM20.1 ISR18: minOppExtension errors wrongly flagged for overlapping via and wire for OR constraints
2486905 The PBSR flow does not work with the environment variables, strobeTime, and maxNumSnapShots
2484051 Grids are not saved when saving images with axes turned off
2480285 Poly fill does not work for PO=135nm area
2479961 Snap to Grid does not work reliably
2475109 Definition of pspice view instantiated in VerilogA is not getting included during AMS simulation
2471025 DC operating points parameters are not shown in the OP Parameters window
2452107 quickAlign minEndOfLineSpacing on M11 when Min Spacing mode is enabled
2450243 PSD plots created by the Spectrum assistant in Virtuoso Visualization and Analysis XL do not have correct unit for y axis
2449716 The info analysis is printed on the netlist even though the analysis types are disabled on the Save Options form
2447496 Auto via generation is slow on metal overlaps
2443100 Change Edit Mode in Schematic XL does not take mixed use of design intents and constraints into account
2441543 endOfLineKeepOut constraint displays only the maximum value of the extensions
2428231 EM Solver assistant needs enhancements to consider for mirrored die placement
2426275 Netlist creation for a Smart View returns _parEv2IDesignGetNetNameOnInstTerm: (PARA-3001) error
2413718 Virtuoso exits unexpectedly: pslNXDB::initReadDatFiler
2360502 Request to exclude the default signal types from the Global Active column in TPA filter session
2327560 Performance degradation observed while stretching objects
2307553 Request to snap pin center to grid in Symbol View Editor
2302557 maeGetVar function does not return a correct local sweep value when nominal values also exist for a test
2298593 Using the Re-run Unfinished/Error Points commands for an ADE Explorer history in ADE Assembler uses the setup from ADE Assembler
2284234 Adding an OCEAN measure file twice adds an empty file when copyMeasurementScripts is set to t
2259585 Abstract generator exits unexpectedly when it is run from a layout cellview on which CLE design partitions are defined
2131280 schSnapToGrid API moves on-grid non-square shaped polygonal pins
2023168 Snap to Grid causes connectivity issues

December 2021

2597936 Monte Carlo simulation did not finish
2595246 calcVal: Dependent points stay in pending mode
2595220 Issues with different signaltype properties between schematic supply nets and wreal supply nets when using Check and Save
2592457 Unable to open the Transient Options form from the Debug environment
2592456 InOut terminal direction is not followed for flagging an unprotected Source/Drain antenna violation
2588720 AMS-UNL Netlister exits unexpectedly when netlisting a config view with Verilog block
2588701 Multiple instances of a warning message displayed to report a common hierarchical Express Pcell
2588056 Netlisting fails with syntax errors but the same design netlists fine with Virtuoso ICADVM20.1 ISR16
2587408 AMS-UNL netlisting of design exits unexpectedly
2586567 Virtuoso exits unexpectedly when running 48 run plan runs
2585407 calcVal: Incomplete run when using dependent tests in LSCS and running in series - points pending forever
2585242 Auto-Create Pins command displays VFP-23004 error when run on labels with connectivity
2584390 Simulation is in suspended mode but ADE still shows running status with LSCS mode
2584286 Virtuoso Power Manager auto-backtracing for simple logic gates is causing the tool to exit on a large design
2584285 Virtuoso Power Manager Boolean optimizer not able to converge in specific cases with a large set of operands (~300)
2584068 Behavior change in Schematics XL license retention
2584041 When netlisting fails in design netlisting there is no useful entry in the Messages Viewer
2584039 Schematics XL retains license after design data is closed
2584008 orthoGrid issues seen with shielding flow
2583524 Is there a way to have Cross-View Checker ignore checking 'Match Terminal Signal Type' with SystemVerilog views
2583431 LSCS using dependent tests and semi parallel run plans causes core dumps to be created
2582147 Incorrect backtracing for hierarchy cells identified as buffers
2581621 axlSensitivitySetMaxContributionFilterSlot causes Virtuoso to exit unexpectedly
2580919 Unexpected spine generated in design without row information
2580773 Spurious cyclic dependency error prevents DC Analysis form from opening
2580233 Via creation is slow for some overlapping regions
2579553 Virtuoso RF Solution exits unexpectedly when Verify Design is used
2579261 Virtuoso exits unexpectedly when using UNL recreate
2579159 Some nets failed to convert when exporting CDL netlist from upper-level schematic
2578674 Remove symbolic links when netlister service copies shared netlist files under the .tmpADEDir directory
2578075 Netlists generated by versions IC6.1.8 ISR21 and IC6.1.7 ISR23 are different from each other
2576935 LSCS fails to netlist points that repeat the view name from the first point of a config sweep in a parametric set
2576909 False violations reported by the minOppExtension constraint
2576759 Plot Results does not work after renaming a history with filter PCD flow
2576381 Binding did not complete because pluArray::sort has duplicates
2576057 Virtuoso ADE Assembler does not provide LBS as Distribution Method after LSF upgrade
2575542 ADE Assembler license checked out when using Layout XL
2575468 Waveform expressions are shown even though they are disabled in the 'Configure what is shown in the table' pulldown
2575357 Ensure that all corners are enabled in the Setup Library Assistant when using the Import from CSV command
2574815 The cdsTextTo5x binary reports an error when importing SystemVerilog files in ICADVM20.1 ISR21
2574775 Moving a pin or a wire object results in incorrect snapping when overlapping WSP tracks are present
2574716 Slowness in displaying a package layout while zooming in
2574659 Virtuoso exits unexpectedly when closing ERROR(ASSEMBLER-2225) message popup in ICADVM20.1 ISR20
2574647 Layout integrity check interprets Hierarchy Range incorrectly during Edit In Place/Descend Edit
2574234 coincidentAllowed parameter is blocked for minSpacing
2574089 Few ports are missing in the Verilog netlist when hnlVerilogTermSyncUp is set to mergeAll in the .simrc file
2574004 Virtuoso exits unexpectedly during import of .mcm file from Allegro
2573923 Setting hnlVerilogTermSyncUp to mergeAll in the .simrc files returns incorrect device names in the Verilog netlist
2573720 Setting termPinLayersForEMCheck causes KCL error in ICADVM20.1 ISR21
2573425 AMS UNL netlisting is slow
2573350 Runtime stack overflow when selecting a large number of signals for node set
2573093 Renamed testbench is not propagated in Corners Setup when using MTS
2572573 Recurring internal application exception in Virtuoso
2572177 Auto via creation is taking too long to place the vias
2571950 Connectivity extractor cannot recognize substrate connectivity when isolated p-well is formed with two distinct layers
2571823 EMIR Analysis Setup: spfchecker file size confirmation slows down Virtuoso
2571512 Post-layout instance names with special characters do not work in Instance column filter of Reliability Report view
2571402 Net Tracer does not trace cross-fabric nets into a die
2570536 Virtuoso terminates unexpectedly on copying a filled dummy cell
2570480 ICRP stopped by ADE with linger time when Job Log under .tmp* directory cannot be removed
2570195 Questions about Cross-View Checker check Match Terminal Signal Type
2570008 VDR flow fails when adding mark instances instead of labels
2569733 XStream Out translation could not complete when translating an invalid OpenAccess object
2569160 Die export errors in the ICADVM20.1 ISR21 version
2569110 VLGen runs automatically when the layout is in read-only mode
2568985 Warning message displays the full list of terminals with missing pins
2568886 Cell values that include non-numeric flags are not treated as numbers for column filtering
2568881 Reliability Report view incorrectly shows results of age_yr multiple times and does not show age_she_yr
2568828 Virtuoso exits unexpectedly when re-evaluating run plan history with reliability simulation results
2568779 Waveform Expression filter not behaving as expected
2567456 Coverage results in Virtuoso ADE Verifier are incorrectly reporting pass points as failed
2566640 Ensure that layer derivation is correct in DRD editing
2566221 Netlisting a variable width bus using the runsv command is reporting errors
2566057 Virtuoso exits unexpectedly
2565983 Autofill for Select Layout View form is not working
2565393 Netlister adds a suffix to instance names when subconfigs are used
2564536 Virtuoso RF Solution-Clarity 3D Solver: Virtuoso exits when generating the ports
2563943 Full netlisting seems to happen for design netlist even though the netlist was copied from .tmpADEDir
2563714 check_windows values are not getting imported
2563635 In Virtuoso Space-based Router, ASIC(MST) is unable to route the M0 rectangles when CM0 trim shape is present
2563606 EAD: Point-to-point info balloon does not display a resistance to the pathSeg created by the Create Wire command
2563427 In ICADVM20.1 ISR21, Virtuoso Space-based Router ASIC (MST) gives incomplete shielding
2563183 Change in behavior of ansCdlCompParamPrim between version ICADVM18.1 and ICADVM20.1
2562912 Changing the trunk width with autoTwig also changes the width of twigs on commit
2562529 Validating Setup is slower in ICADVM20.1 ISR21 compared to ICADVM18.1 ISR13
2561864 Multiple Express Pcell warnings received about excluded sub-masters
2561273 Specification does not update following re-evaluation with new history management
2561268 Virtuoso RF Solution-EMX Solver: Via Connectivity issue when using metal resistors
2561223 Improve quadratic runtimes in RC extraction
2561076 Virtuoso ADE Verifier fails to connect with vManager when it is restarted after disabling the vManager setup
2560422 Check Against Source displays only single m-factor nfin change in Annotation Browser
2560415 Color mismatch when creating synchronous clones
2560278 Provide post via placement trigger to repeat the Create Via operation
2559427 Origin and rotation changes for Modgen figGroups during Update Components and Nets
2559354 Virtuoso Chip Assembly Router is not working with Virtuoso Layout GXL tokens
2559212 Auto via creation operation does not fill the entire area of overlapping shapes
2558849 AutoVia stops responding and does not interrupt or return when using Ctrl-C
2558577 Unable to launch Virtuoso when the first directory of CDS_LOG_PATH is not writable
2558240 Virtuoso exits unexpectedly when reloading current subwindow in Virtuoso Visualization and Analysis XL
2557913 Runams does not copy the reference Verilog file in Hierarchy Editor when using SystemVerilog
2556398 In Pin to Trunk routing, vias are placed in the wrong direction
2555203 Resistance path cannot be recognized for a net even when the instance has a pin
2554935 AMS UNL netlister not generating the netlist with a large parasitic extracted view
2554629 Sanity Checker does not report missing VDR labels on certain internal nodes
2554025 Voltage labels cannot be created for certain internal nodes
2553548 Evaluation errors on points where the simulation has finished with errors
2553474 Setting the ignoreDesignChangesDuringRun environment variable incorrectly adds checks.scs in ADE simulation files
2553422 Virtuoso ADE Verifier is not overriding the job policy set in Virtuoso ADE Assembler
2553174 Virtuoso RF Solution: EM extracted view fails with excluded cells
2552279 Calculated values of eye height and eye width are wrong for PAM4 eye diagram
2551840 Adding referenced implementations to implementation sets is not working as expected
2551839 Allow the exported JSON file to contain histories for all implementations within an implementation set
2551402 Add a safeguard into netlist service for incomplete beanstalk communication
2551074 AMS UNL netlister results in a SKILL error when using an extracted view
2550257 Need an exclusive lock on a category in Virtuoso
2549927 Reconsider the need to do full re-netlisting for config sweeps
2547053 Virtuoso stops responding when VDR simulation is run for large datasets
2546691 Backannotation for DC operating points not working with AMS simulator
2545162 Negative cpk value(Yield View) when spec is set through variables in maestro even though all results are within the range
2542265 maeSaveSetup() not honoring the design management lock status
2541393 Virtuoso exits unexpectedly when using OutputSetupProxyModel
2540449 Make Group not creating Modgens in the Auto Place and Route flow with aprCreateModgens environment variable set to t
2539397 Improve the error message displayed when multiple spaces are assigned to the same implementation
2537427 The ahdlUpdateViewInfo function is taking time to update the cellviews
2529142 Virtuoso Space-based Router creates unnecessary jogs and bends even though there are nearby tracks available for it to make a straight route
2527554 Division by zero results reported as V in results view
2526880 Yield view is empty after Sort
2525396 Virtuoso ADE Assembler errors (EXPLORER-2225, EXPLORER-2200, EXPLORER-8010) reported in each migrated ADEXL state
2512652 Virtuoso exits unexpectedly when using op function in the calculator and then clicking on the schematic
2512626 The Remove Pre-Route Dangles in Virtuoso Space-based Router removes the objects outside the partition
2512621 Allow the first column in the 'Show Differences in Requirements for File' form to be resized
2511307 viaStackModel::generate should not apply maxWidth to the biggest length of a shape but to the smallest
2502685 Groups formed after creating synchronous clones are off-grid if the label of the instance is the outermost data point
2487228 Waveform expressions are shown even though they are disabled in the 'Configure what is shown in the table' pulldown
2484381 Remove uniModeSpectreX from the ADE Explorer user guide
2481204 Waveform plotted by loading a VCSV file does not show all data points when symbols are turned on
2475200 Schematic Creation from SiP File flow error-no component definition found
2470944 Grouping corners impacts additional model files
2449985 Spectrum plot does not show all data points when Style is set to 'points' and 'Show All Points' is enabled
2437436 Virtuoso Chip Assembly Router is not working with Virtuoso Layout GXL tokens in IC6.1.8 version
2435101 Instance terminal keeps signal type of previously connected net
2413216 Targeted Enforce does not work with path shapes
2359747 Waveform expressions are shown even though they are disabled in the 'Configure what is shown in the table' pulldown
2359745 Waveform expressions are shown even though they are disabled in the 'Configure what is shown in the table' pulldown
2358152 axlToolToggleSaveOutput causes Virtuoso to exit unexpectedly
2351601 Add a checkbox to enable or disable corners in the Setup Library Assistant
2333051 Shapes in SIP exported using area transfer rules scaled when DBUPerUU of die footprint and package library are different
1926476 Property Editor layer list disappears when moving mouse over layer
1772798 Property Editor assistant loses focus when mouse moves out of the assistant window
1515439 rodCreatePath fails when size is less than or equal to 7
1496725 Property Editor assistant applies change when cursor moved out of assistant
1435382 How to stop committing changed parameter by moving mouse cursor away from Property Editor
1248334 Property Editor saves text changes without clicking

February 2022

2622713 Checker generating orthogonalPair parameter warning for minSideSpacing constraint
2616891 Shielding created using Tcl gives unexpected result in ICADVM20.1
2616544 In LSCS mode, reliability simulations do not run in parallel
2615855 Bus nets with split ports are not printed in Verilog netlist
2615751 View name is added as suffix to subckt name
2612741 Spectre argument +param does not get translated for cloud runs
2612738 Re-evaluation not working for cloud runs
2612181 Virtuoso Layout XL exits unexpectedly when 'Connectivity – Update - Components and Nets' is used on a cellview
2611135 Save a Copy adds the files with cached links for test_states directory
2610826 Provide utility for scanning and cleaning up duplicate constraint members and unreferenced constraints
2610457 Error (xmsim: *E,PVHILC) incorrectly issued for a schematic instance in the design
2610352 Corner overwrite does not work if the corner value is 0
2609958 Difference found in the reporting of incomplete switch_function and isolation enable condition
2605626 Quantus execution exits due to the LVS option LAYOUT CLONE TRANSFORMED PLACEMENTS YES
2604614 calcVal: Eval error when using expressions with evalType sweeps
2604333 Extra point added to a non-Manhattan segment during XStream Out translation creates a sliver in a complex polygon
2603003 Evaluation error when using calcValForRel with evalType = sweeps
2602853 Summary tab in the EMIR Analysis Setup form does not include the static current file information in the emir.conf file
2601933 Virtuoso Power Manager extraction incomplete or missing pg_function for a design
2601744 Provide better support for HiDPI displays
2601273 Results database broken in ADE Assembler when using calcVal
2600806 Inductor Pcell layout is different between IC6.1.8 ISR15 and IC6.1.8 ISR22
2599779 Virtuoso MultiTech Framework exits unexpectedly during Generate from Source when die abstracts include annotation shapes
2599678 Diffusion width not available on the backside terminal
2599201 Using Stretch command with Keep Wires Connected to: All wires and vias selected modifies the via stack and makes a cut layer and metal disappear
2599178 Re-run unfinished points does not work if the MC history item contains eval err on some outputs
2598755 stretchViaMode not synchronized with the Via Mode option on the Stretch form
2598173 Coupled supplies issues in the user-defined macro flow
2598171 pg_functions issues in the user-defined macro flow
2597880 Results lost with moving history to read only
2597541 Virtuoso exits unexpectedly when using Direct Plot in Virtuoso ADE Assembler
2597231 LSCS: Aged reliability simulations are not using the Max Jobs setting, they run one at a time
2596871 Cancel button on Area Estimation Parameters form does not stop Auto Generate Hierarchy command
2596537 Unexpected netlist error with calcVal output expression and VAR() for temperature
2596440 Protection device should be recognized by virtue of correct signal type propagated on top-level pin shapes
2596164 Noise Summary window does not open after pnoise analysis when noisetype=sampled
2596157 Unexpected via variants are created during routing
2596139 Cannot stretch a segment of an FGR
2596129 Error SCH-7289 reported when exporting CDL
2595415 Add the instance occurrence count in the cell type table for easier identification of a user-defined macro
2595366 Update the helper API to include the new environment variables
2595357 allowedSpacingRanges with jointEOLWidthRanges flags false violations with multiple entries in table
2594911 Backside credits are not available on the terminal
2594780 Unreasonable behavior of re-run in Monte Carlo analysis with corners
2594720 The dcmode=aps option for Spectre X does not appear in the xrunArgs file created for AMS simulations
2593963 Foundry-specific keyword causes column filtering to break in Reliability Report view
2593938 eval error with getAsciiWave in outputs
2593929 Unexpected SKILL file locking behavior on .il files
2593808 Virtuoso exits when the Clarity 3D Solver is invoked from the Electromagnetic Solver assistant
2593340 OpenAccess scan errors when exporting CLF from the Electromagnetic Solver assistant
2592763 Some minSideSpacing violations are missed by the checker when jogs are present
2592214 Restore the resolution for Track Pattern color4
2592097 HDL package setup is not read if no text view is used in config view
2592053 Virtuoso dot pins display switches from 45-degrees to 90-degrees as zoom changes
2591375 AutoVia fails to create via stacks in some cases
2590782 OVERLAP property is inconsistent after LEF Out translation
2590392 None of the simulations start with ICRP when VAR is used in Model Section
2590277 Netlist looping issue when a Run Plan history is rerun
2589772 lceGetFracturedShapes SKILL function returns 'nil' when cellview is open in non-graphical mode
2589613 The flip mechanism does not work for certain designs when running assisted move
2589371 Pin to Trunk routing gives unexpected results for a segment when connecting device pins to a user-defined trunk
2589115 AMS UNL netlisting does not work as expected with the specified custom netlist procedure
2588973 Incorrect coverage calculation in ADE Assembler
2588759 Merge command must use conic sides for merging circles and rectangles
2588669 Display the net name during drag operation when snapResizeWireObjects is enabled
2587998 Slotting issue when running sltShapeConsecutiveSlotting on via stack
2586955 Literal stack overflow occurs when running the Load LSW Info command
2585875 Slowness in display when zooming and panning in a new design
2585832 CLASS BUMP keyword being incorrectly applied
2585351 AMS UNL becomes unresponsive during incremental netlisting
2584157 Stretch command not working for pathSeg that has via enclosure smaller than wire width
2583395 Export die needs to test the text coordinate and value to match the pin and instTerm over the bump or pad
2583394 Die audit needs to test if the text associated with the pin is over the pin
2583357 Save button in ADE Assembler to be grayed out in IC618.ISR21
2582853 Expression fails to evaluate when using the eyeAperture function
2582708 The probe.tcl file generated by runams does not include the outputs defined in the maestro view
2582182 Improvements in error messages
2581969 Issue in dependent variable expression evaluation in the netlist created by a 3rd-party simulator
2581848 Display level not updated in a new layout window when using the Shift + F bindkey
2581558 DSPF out-of-context probing fails for a few samples of Monte Carlo Sampling
2581226 Bottommost histogram displays off the screen, not legible
2581203 Segmentation fault when running simulation in batch mode
2580123 Virtuoso exits unexpectedly when returning to the top level after Edit In Place operation
2578760 Cannot use iterated instances with DSPF-based AMS simulation
2578599 Unable to stop an interactive AMS simulation until the SimVision console comes up
2578521 Virtuoso exits unexpectedly because of segmentation faults in rdbLoadResults
2578041 OSS netlister adds a suffix to all cell names if duplicate cell names are found during incremental netlisting
2577720 Notify when a variable in the EMIR Analysis Setup form isn't set properly or the path specified through it does not exist
2576985 Unable to backtrace if customLogic cell is in the backtrace path
2576409 Ocean script does not support dynamic parameter sets
2576176 When ADE Assembler has more than 1400 rows of output expressions, expression evaluator gets stuck indefinitely
2575857 hnlVerilogTermSyncUp=mergeAll should not expand the wire labels when connecting ports by name
2575220 Wire cannot move to adjacent WSP with zoomed area
2574178 lceAddSimpleStopLayers SKILL function does not release the checked-out Layout XL license
2574145 Routing tracks belonging to a cell are incorrectly left at the top after a Make Virtual or Make Cell run
2574129 Cannot use runams with a maestro view that has a Tcl file specified for it
2572604 Optimize the mechanism to automatically resize column width in HTML reports
2568910 What can cause the save button in ADE Assembler to be grayed out?
2568325 Improve routability check to report accurate and consistent results for any pin accessibility/routability issues
2566071 Run Preview does not honor point selection
2563722 Dynamic Display does not recalculate resistance with the Create Wire command
2563074 MTS setup issues simulation error if MTS block contains instances that use same cell but different view bindings
2562646 Netlist error when Monte Carlo Sampling run uses ICRP job control mode and LSF distribution method
2561101 Enable a timestamp check on histories and results loaded in Virtuoso ADE Verifier and notify if results are out of date
2560148 EMIR Analysis Setup: time window out of transient span error
2558968 Include option to issue warning/error when a DSPF file included via dspf_include is not being used in simulation
2558964 ADE netlists with _schematic in the subckt name causing dspf_include to not take effect
2550710 calcVal not working correctly for waveforms when evalType is sweep
2548024 Improve the error message that is displayed when the -state option is used with a maestro view
2543605 When spec is set, the Plot command fails to plot the waveform results of expression v()
2542009 Unable to set the fields, nportirfiledir, nportcompressfiledir, and nportbbfittedfiledir using the VAR syntax
2541046 Voltus-Fi is reporting a 200x600 via as a 600x200 via
2540839 LEF In translation incorrectly claims that OpenAccess database has another different via definition with the same name
2540314 Voltus-Fi cannot get the correct factor from the multiple lifetime side file
2538001 Voltus-Fi is using excessive RAM
2531909 Virtuoso Power Manager user-defined macro flow extracting and exporting different or incorrect pg_function
2531198 Found differences in the antenna diode related power pin and related ground pin for a design containing user-defined macros
2527873 Voltus-Fi CCL option extract_dspf -PGNets errors out when the number of nets is very large
2526447 User probe trigger not called when a probe is removed from schematic using RMB menu from the Navigator assistant
2526238 In maestro cellview, the Save a Copy form adds the files with cached links of checked-in state
2525866 dspf_include flow does not work as expected when the subckt name is changed in the schematic netlist
2525553 Encrypted Virtuoso AMS IP Export Reuse flow produces a broken netlist
2525253 The Max Resistance constraint does not work for multi-resistance paths of the same pin
2523565 Show Only Failed Nets does not work with JACRMS_SH
2522998 Reliability parameters are not shown correctly in results database API when they are changed in reliability setup
2522594 Wrong save statement syntax in amsControlSpectre.scs when bus pin inside verilogA block is saved
2521593 Subcircuit in spice netlist for cell names starting with an integer get auto-renamed by HspiceD/Spectre simulator
2520999 Generate Selected From Source command not working for a split symbol
2519711 Random Load Balancing Service initialization failure with EXPLORER-1932 error
2519265 Save the 'Open File' or 'Configure' setting for Stress Test in the Reliability Analysis Editor form
2519170 WARNING (EXPLORER-4030): Invalid MATLAB script, does not have a .m extension
2519052 After the output expressions are sorted in ADE Explorer once, they cannot be rearranged
2516154 Add a possibility to filter through design point ID in the access function axlReadHistoryResDB
2509699 Track Pattern Pull-Up is causing unaligned region track
2509150 Virtuoso exits unexpectedly when using Direct Plot
2505219 Suspending all jobs after some jobs have already started keeps the jobs running in spite of the cancelation
2502577 Adding a suffix to the subcircuit name in the netlist is breaking the dspf_include flow
2490326 The placer tries to chain passive devices and reports message LX-2235
2467446 Add the ADE Assembler Reset Table button to ADE Explorer as well
2455686 OSS netlister adds a suffix to all cell names if duplicate cell names are found during incremental netlisting
2440012 calcVal in ocean script is not evaluated correctly
2432200 The view name gets appended to the subcircuit name unless the netlist is recreated
2414230 The dspf_include flow does not work as expected when the cellviews are not named 'schematic'
2343743 Unable to move outputs once sorted using the column header in the Outputs Setup tab
2308508 Netlist created for the same cell in different libraries using NC-Verilog environment prints the subcircuit name with a suffix
2265844 calcVal in same test and eval type MAS gives incorrect result with sweep defined in Global Variables
2204373 Clarify the behavior of calcVal in the context of measure across sweep
2189768 Improve the performance of coverage calculation while saving the setup library view
2118660 Cannot run the dynamic paramset simulation from an OCEAN script
1963429 Netlist created for the same cell in different libraries using ADE L prints the subcircuit name with a suffix
1962107 Coverage is not automatically saved with the ADE Verifier cellview and needs to be recalculated
1949290 Add the 'Reset table to display per-test evaluation order' button to ADE Explorer
1910483 The input.scs file generated after setting sevNetListAndRun() prints the view name as a suffix of the subcircuit name
1689303 Netlist generated during incremental netlisting prints the subcircuit name with a suffix
1618890 The dspf_include statement prints the cell name with a suffix when the same cell name is used from different libraries
1593665 Using the Create Netlist command appends the view name to the cell name as a suffix when the simulator is set to Spectre
1592892 The netlister adds a suffix to all cell names if duplicate cell names are found
1066316 Netlister is adding view name to cell name in instance-based binding

March 2022

2662741 Simulation stays in pending state when using the calcValForRel expression in the reliability setup
2661865 Delta marker label cannot be moved in IC6.1.8 and ICADVM20.1 ISR25
2661646 Incorrect calculation of maximum eye height and maximum eye width
2658601 Connectivity extractor for bundle nets with repeated bits not working as expected
2658158 Cannot initialize SRR license
2657538 Performance degradation in LSCS mode when RDBSynchronous is set to Full
2657528 Schematic behavior has been changed for multi-bit wire names in IC6.1.8 ISR25
2656127 Routability check reports incorrect spacing violation message for a short between pin and shape with different connectivity
2655960 LSCS has requirements for additional slots in session class for third-party simulator
2654780 Error when viewing or highlighting the violations of Checks/Asserts
2650842 Performance degradation in LSCS mode when RDBSynchronous is set to Full
2650571 Die export returns dbConcatTransform error when using the area transfer file option
2650526 Incorrect GDS file created during XStream Out translation with many vertices in IC6.1.8 and ICADVM20.1 ISR24
2649981 Routability check is not reporting pin access issues accurately
2649976 Routability check reports false spacing violations
2649138 Virtuoso Space-based Router reports a warning for missing route elements in the ctuRoute function
2649106 XStream Out creates a corrupt GDS file in IC6.1.8 and ICADVM20.1 ISR24
2647505 Virtuoso exits unexpectedly when you run ‘unlock all’ for the colors
2645779 Area estimator reports inaccurate area as it prefers signal nets during merging
2644604 HighCurrent design intent push-up from lower level fails when the top-level net is internal
2644577 Virtuoso stops responding when running a Monte Carlo simulation
2644274 Reliability analysis gets enabled automatically when the EMIR Analysis Setup form is opened
2644239 Virtuoso Visualization and Analysis XL exits unexpectedly when loading a .grf file with PSF selected as results database
2644210 Ensure that the calcVal upfront error check considers the run plan correctly
2643854 Incorrect tooltip on the Fault Level field in the Fault Rules form
2643798 Virtuoso exits unexpectedly due to segmentation faults in dalAliasMap::setDataChangeStatus
2643501 LibImport should ignore the technology file attachment of a pre-existing library and reassign the technology file to itself
2643177 Virtuoso exits unexpectedly when plotting AMS results during simulation
2642784 Oblong-shaped IOs have wrong orientation when exported to Clarity 3D Solver
2642587 Stretch command moves pathSeg outside a design partition
2642351 Diffstbprobe OCEAN script is not netlisted correctly and causes a simulation error (SPECTRE-16850)
2642347 SDR cannot start a stranded wire from another stranded group of wires
2642330 Virtuoso exits unexpectedly when using the Stranded Wire command in SDR
2641800 Change in design message should be displayed in the customer environment
2641318 Stranded Wire does not drop vias on pin when Current Estimation Mode is 'Nearest Island Current'
2639786 axlExportOutputView does not return the Checks/Asserts results on the first call
2639191 Signal Type should be set as value of reference view when executing Update Pins From View
2638963 Power router creates an empty fig group if power stripe or via creation fails
2638895 The form that defines the layer width/spacing constraints should be closed along with Pin Accessibility Checker form
2638825 Quantus av_extracted view missing multi-cell placed device properties
2636502 Multiple pop-ups block the screen when an EMIR simulation is run
2635968 Post-processing of the Checks/Asserts violations returns errors
2635921 XStream Out translation results in a large number of polygons and the DRC test shows non-orientable polygons errors
2635537 Issue in pg_function extraction if _vpmEnableBaseSupTracingThruShort is set
2634615 Either output expressions or MATLAB scripts return error in the Results view
2633495 Virtuoso RF Solution-Layout Versus Schematic Driven Flow: Issue with LVS database reader
2632751 Halo difference between IC6.1.8 ISR17 and IC6.1.8 ISR18
2632185 The termMapping CDF property of the ibit symbol in analoglib is set to an incorrect value
2631591 Virtuoso VDR menus do not end with ellipsis
2631586 Creating a wire using the default color option does not reflect the mask number correctly
2630886 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2630480 Cannot create ports for all components in a design
2630439 Selecting 'Show selected Cells' removes already selected boundary cells
2630364 Vias placed on shield are not aligned and causes cross topology
2629961 Edges of row in chopped rowRegion are not aligned with ndiff/pdiff WSPs
2629776 Layer sets handled incorrectly if the same path is specified multiple times in setup.loc
2629092 When creating a new layout with auto routed nets with shields, shield nets are not routed
2629068 Allegro Import and Allegro Export roundtrip scrambles orientation of oblong-shaped die IOs
2628824 Fault dropping flow does not work when using layout-based fault generation
2628733 Lock Unselected Vias is not respected correctly in ICADVM20.1 ISR24
2627984 The CAS tab in Annotation Browser does not display all results
2627763 Virtuoso exits unexpectedly during automatic shielding creation
2627625 Pre-run script ignores parameterization in ADE Assembler
2627324 The is_unconnected attribute extraction must be enhanced
2627298 Virtuoso Power Manager should only add the is_isolated attribute when all the connected nodes are already connected to isolation cells
2626414 Unable to generate an ADE netlist in the first attempt; works fine on recreating it
2625740 Device M5 is not running TRP with pdk2trp selection
2625470 Unable to launch Virtuoso when virtuoso201.conf.lock exists in $HOME/.cadence
2625116 Plotting dB20 in Virtuoso Visualization and Analysis XL and from the Direct Plot form creates different axes and units
2623708 Include molding compound definition in Virtuoso RF Solution and Clarity 3D Solver cross-fabric flow
2620957 Cannot sweep the value of a device parameter in a pre-run script
2619960 The Virtuoso Schematic Editor L license is not checked in when a text view is closed
2619409 Row snapping for multiple heights snaps devices outside rows
2619036 Virtuoso stops unexpectedly while loading history
2616530 Unable to exit Virtuoso in nograph mode due to corrupt lock files
2616521 Differences in routing when the pre-routes are part of the route when compared to the case when pre-routes are not part of the route
2616066 The spectre.opts tranFilterExtreme variable has no effect on the GUI in ADE Explorer
2614969 In ICADVM20.1 ISR23, ASIC(MST) fails to route mustJoin pins in a single row
2613222 Outputs with MATLAB scripts return errors when simulating multiple corners
2612730 Checks/Asserts results are not displayed when a simulation is run on cloud
2611868 Virtuoso Power Manager is unable to resolve pg_function and issues the LP-3082 warning
2611218 Allow running stb analysis with transient analysis for AMS without the need to enable ac analysis
2611122 Unexpected cyclic dependency detected when a global variable disabled for the test causes this dependency
2609614 The Voltus-Fi result database gets prefilled instead of the emir0_bin file
2608278 Virtuoso SystemVerilog Netlister is netlisting concatenated bus port connections incorrectly
2606229 DEF In translation does not map some vias to standard vias
2606214 MATLAB output expressions fails to evaluate for all corners
2604655 Asymmetric capacitor extracted in a fully symmetric structure
2602732 Virtuoso becomes unresponsive when running commands related to a constraint view
2599759 Incorrect temperature values when using a different variable name than temp
2596137 Iterated instances with modgenUseIteratedAsMfactor==t can result in non-synchronized GPE text pattern symbols and layout views
2595164 A device parameter expected to use a design variable uses a global variable instead
2586084 Generate All From Source should not create level1 design intent constraints if a layout master for an instance exists
2580925 Weird units are displayed in the Highlight legend for Self-Heating Effect
2579964 Abstract step does not create pins from all labels if textDisplays are present
2578528 Allow local variables to overwrite global variables when used in conditional statements
2573381 Variable dependency is lost in the netlist when the variable expression uses sqrt
2571549 Performance issue with a large number of model files due to a time-consuming call to the _axlGetDDSPFFilesInModelFiles function
2565603 Virtuoso Schematics XL license should not be checked out when working in Virtuoso Schematics L with a schematic view that contains design intent
2554348 Allegro Export must check that the view type is set to layout before exporting to Allegro
2553495 Unable to create statistical corners when the Save Simulation Data and Save Netlists options are deselected
2545473 Selecting Extend Fill on the Fill tab of the Auto P&R assistant results in the fill area extending beyond the row region
2542152 AutoCopyCellviewVars not honored if the test is associated with a config view
2535317 VAR() in the Temperature row of reliability analysis in not working as expected
2525044 Method to reset the spacing value using Constraint Editor should be simplified
2523773 Filter ignored in the maeExportOutputView command for the second test
2519581 Unable to set different values for the bandwidth parameter through design variable
2509056 AMS UNL netlisting fails intermittently when using VAR syntax to define an argument for the xrun command line
2502058 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2501660 Plotting results in Virtuoso Visualization and Analysis XL is taking much longer than expected
2497872 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2496772 Net capacitance for some nets is not displayed in Capacitance results view
2321187 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2309400 Failed to dump WSP using the wspDumpToFile function
2284554 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2278051 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
2010461 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1942685 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1562579 setup.loc mechanism incorrectly creates duplicates of layer sets
1491057 Support parameterization with a pre-run script
1394928 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL
1320420 Cannot sweep the value of a device parameter in a pre-run script
1271751 Layer sets handled incorrectly if duplicate paths are specified in setup.loc
1248065 Layer sets appear twice in the Layer Set Manager if layer set files are saved in ~/.cadence directory
1046032 Swept parameters are not passed to the pre-run script
1042229 In ADE XL, instance parameterization is not supported in the OCEAN pre-run script
910654 Support annotation of scalar outputs in Virtuoso Visualization and Analysis XL

July 2022

2705960 Virtuoso NC-Verilog Environment must sort inout bus ports in alphabetical order after re-extraction
2704219 VDR flow: netData table is empty if the tab name in Annotation Browser is not HVDRC
2704162 Evaluation error for eval type sweeps when more than one corner is enabled
2702874 1801 Import fails because the 1801 file has multiple create power domain statements with the update argument
2702376 VAR statement returns an error when config sweeps are added to the setup
2697515 The 'Download Cloud data after Run finished' option in Save Options is not available for run modes other than Single Run, Sweeps, and Corners
2697499 Virtuoso stops unexpectedly when running Monte Carlo on AWS cloud
2697431 runams IP export: memory leak issue
2696289 Virtuoso exits unexpectedly when using the Schematic flatten command
2695888 VAR function is not being evaluated when running a simulation with EAD enabled
2695684 Import csv does not work in User-Defined Statistical Variation Setup
2694887 Update net connectivity sets the -create_guides to false if -honor_valid_routing_layers is true
2694840 Virtuoso stops unexpectedly while running HBAC analysis
2694441 C mismatch in EAD Browser when comparing C-only with RC extracted DSPF netlists from Quantus QRC
2693877 CDL Out prints unnecessary instance parameter when the parameter value is set to nil
2693413 Netlisting is slow when corners have numerous sweeps
2692634 The save option 'Download Cloud Data after Run finished' is not retained in the form for Monte Carlo run
2692543 Virtuoso launched via bsub with cdsroot/bin/virtuoso gets netlist error 'Failed to create MAPI session' in RPC mode
2691969 Virtuoso ADE Verifier stops responding when multiple implementations are running in parallel, and the 'Reload Simulation Results' button is clicked
2690880 DRD checker gives false orthogonalWSPGrid violations leading to AutoVia failures
2690670 Custom parasitic parameters in SmartView DSPF are netlisted incorrectly
2689556 Calculator cannot access a design variable with config sweep
2688870 Evaluation error for eval type sweeps when more than one corner is enabled
2688244 The autoGenHierStopViewsForLib environment variable in Auto Generate Hierarchy supports wildcard character
2687888 Fault generation fails when running fault group with faults referencing global nets
2687886 Need performance improvement in Virtuoso SystemVerilog Netlister
2687296 Virtuoso exits unexpectedly with leLayerSize
2686760 The router ignores the global bias when routing.
2686073 Add support for global bias defined by congestion analysis in route selected (route_optimize) net
2685402 Accessing the Quantus menu results in the '_leQrcLoadContext: too many arguments' error
2684927 Spectre netlist displays an incorrect analysis name when multiple info analyses are specified
2684714 Spectre simulations in Virtuoso ADE environment plot incorrect waveforms when the order of terminal names and nets is mismatched
2683169 Incorrect transient voltage annotations are displayed when expandIteratedInstanceBusForAnnotation is set to t
2683082 Run summary data file incorrectly reports No Results status for requirements
2682601 The Update Layout Parameters command deletes instances
2682441 Fix slight device shift and backward devices movement observed during Modgen interactive device move
2681981 Error OSSHNL-202 is incorrectly reported during netlisting despite of sufficient disk space
2681862 Abstract Generator does not work correctly when the library file is not named "cds.lib"
2681615 Running Update From Source on virtual clones is generating devices at the wrong hierarchy level
2681600 Clone synchronization is lost after edits are made on virtual clones placed across the design hierarchy
2681324 QuickAlign in partial selection mode causes wire to disappear
2680346 Virtuoso SystemVerilog Netlister does not rename a module if its name contains 'module'
2679815 Add an option in Voltus-Fi to calculate the length and width parameters from the bounding box for third-party DSPF
2679246 VDR places voltage labels for irregular pins in the center of the boundary box of the subcell pins
2678959 Virtuoso ADE Verifier must use the external program name specified in preferences to launch child processes for project directory setup
2678681 Error occurred in Fault Simulation with ICRP process
2678602 Cannot backannotate the current for multiplier MOS instance with aelSumOPParam from an extracted view simulation
2678350 Setting maeUpdateWindowTitle to t causes a slow start up with ICRP
2676752 Peak and RMS value of HighCurrent design intent does not split on the Profile Current of glyph
2676328 GDB command related warning message is displayed when starting Virtuoso
2676007 Fault point that errored out due to faultlimsteps does not show up as sim err and is not treated as Undetected
2675600 Regular expression used to add the reference suffix fails for signal that have '_L' or '_R' in their names.
2675400 Coverage is incorrect if there is retried simulation for some faults
2675128 Copy statistical parameters data from one corner to all corners on CSV export
2675113 Modgen array instances in the last row are not aligned
2674970 Since ICADVM20.1 ISR20, via array spacings become zero when tapping with a wire
2674951 In a third-party simulator, expression evaluation for a Monte Carlo run fails because vds keeps restarting
2674920 Backannotation Flow is adding instances on schematic in Read mode even when 'lxDummy' is not set to 't'
2674117 Incorrect yellow highlighting in the output expressions for noise analysis
2674033 Need to remove the sweep variable limit for the Noise Summary form
2673605 Unable to plot waveforms in ADE Assembler
2672975 AMS ignores the stimuli file if the suffix is .txt instead of .scs
2672966 Deleting all schematic dummy instances does not restore the ignore property
2672811 The Back Annotate – All Dummy Instances command does not work well with clones
2672001 Auto-resume option for a suspended AMS simulation is not working due to low disk space
2671791 Virtuoso exits unexpectedly when view name is changed in Hierarchy Editor
2671257 Netlisting issue when multiple maestro views are open
2671148 Virtuoso RF Solution-EMX: proc file viewing issue because proc file is not being updated
2670052 ADE Assembler UI freezing after clicking Run Simulation; no way to recover the session
2670034 updateTitleToReflectUnsavedChanges results in an error during netlisting when using parameters in some cases
2669954 Improve the CALCVAL(4) debug message
2669278 Performance issues with axlRunSimulation
2668457 Layout design is not 100% Layout XL complaint even after establishing all connections in layout
2667616 adexl view converted into ADE Assembler results in eval err
2667146 Prevent off-grid violation on metal slots created on 45-degree objects
2665820 ADE Assembler becomes unresponsive after running simulation
2665197 Cannot control cell orientation using the orientation constraint in Virtuoso Custom Digital Placer
2663177 Remove the incorrectly set instrument_module attribute from ahdlLib Verilog-A models
2661991 Remove the Allegro kits containing executables from the ICADVM20.1 build
2659522 Virtuoso Analog Design Environment must automatically resolve OSSHNL-153 error
2658138 Slow loading of a maestro view
2658134 Virtuoso becomes unresponsive after starting a simulation
2657204 In ICADVM20.1 ISR25, EAD adjusts current even for nets with complete connectivity
2655582 Error OSSHNL-153 is reported when the design is switched from config to schematic
2655413 Vias listed in the Create Via form in auto mode are not refreshed when the alternate constraint group is changed
2655334 Pre-EM check mode in EAD flow does not allow the usage of the VAR function for transient stop time
2654386 ADE Assembler goes into infinite loop with a lot of error messages on calcVal
2653018 Virtuoso RF Solution-EMX: Check and report overlapping ports in the Electromagnetic Solver assistant
2652743 Virtuoso stops responding when exporting results data for Checks/Asserts - Device Checks
2651469 Virtuoso exits unexpectedly with SIGSEGV signal
2651061 Slow start of simulations
2650397 Cannot plot the current values on running a transient analysis with the actimes field set to ac in Spectre AMS Designer
2648308 Change arrow direction depending on current flow for HighCurrent design intent
2648163 Area Estimator is enhanced to support a Pcell with pPar parameter
2646488 Noticeable slowness in short simulations run from a maestro cellview
2645961 Symbol view Edit Object Property form does not honor All Selected option for modifying Signal Type attribute
2641639 Virtuoso exits unexpectedly when a simulation that is running for four days is stopped
2639042 Abstract Generator displays incorrect results if the PinsTextPinMap field specifies only a layer name with no purpose
2636481 Error occurs on selecting the “Create Pin on Connected Shapes” option and pin is not created
2634677 Unresponsive LSF jobs do not let the process exit after a Monte Carlo run
2629802 User-defined columns in the outputs are impacting the re-evaluation performance
2627245 Netlisting issue with CDF termMapping and dspf_include
2613686 Extracted view generation fails to connect resulting s-parameters to an iterated instance
2611982 Virtuoso Analog Design Environment must automatically resolve OSSHNL-153 error
2605719 Virtuoso is unresponsive for a significant time after the perEmCheck.log report has already been written
2594043 Enabling EAD mode does not allow the usage of the VAR function for specifying the transient stop time
2593344 Errors when trying to stitch electromagnetic results into an iterated instance and bundled net
2591579 The 'Browse s-parameter file' button in the Edit Object properties form must not resolve symbolic links
2590983 Adding expression units in Output Setup requires saving Monte Carlo waveforms to allow plotting
2582761 With Reliability analysis and Run Plan enabled, age simulation errors out with SPECTRE-16837 message for an unknown reason
2582030 Virtuoso ADE Verifier is computing coverage incorrectly
2571390 The Freeze Columns command in Results tab leads to misaligned rows
2569307 SQL error in terminal while running simulation with Reliability Analyses and Checks/Asserts enabled
2557493 License error behavior is being reported in CIW and not the terminal
2554116 Add support for maxWidth constraint in Virtuoso Space-based Router
2547659 Virtuoso stops unexpectedly when DC sweep waveform is plotted from results in psf format generated by ADE Assembler
2541491 Direct Plot of nets from a smart view created from an iterated instance in the DUT does not work
2540854 Avoid HighCurrent design intent without reference pin when deleting the source sink terminal
2516453 Virtuoso stops unexpectedly when running axlExportResultsViewClickSlot
2213354 Design Intent: DI Main window is disappearing into background (ICADVM18.10.080)
2054435 Fix Voltus-Fi GUI to pick the correct scale factor when multiple resistors are selected using the scale_res command during what-if ECO analysis
2028937 Via shapes should be checked by the WSP design checker when display via shapes is selected
1909157 Unable to view the noise summary on running a parametric analysis with more than four variables
1768936 Backannotation of dummy device should not be working with schematic in read-only mode

October 2022

2723084 Tungsten view cannot be opened if Maestro view is opened first
2722521 Virtuoso exits unexpectedly while creating buses
2722466 Virtuoso exits unexpectedly when running multiple simulations parallelly
2721229 Virtuoso exits unexpectedly when creating bus with odd multiple of manufacturing grid
2720542 Allegro Export translator fails for large text block IDs in libImported component and does not create the DEF symbol
2720030 VDR creation to support schematic iterated instance names with <> Userdv constraint map to layout instances with ()
2719815 The Run button in IC6.1.8/ICADVM20.1 ISR27 fails to start the simulation and gives an error
2719500 Virtuoso exits unexpectedly when loading the EAD setup
2718549 Message Assembler-13059 is incorrectly displayed when showNameHistoryForm is enabled
2717530 Cross probing does not work when using capital and small letters in the hierarchy prefix
2715956 Virtuoso EM Solver-EMX: Distorted Exported polygon
2715433 Virtuoso becomes unresponsive when using to Wire Editor
2715245 Synchronize the behavior in Explorer and Assembler for parameterization of temperature by using the VAR expression in the Setting Temperature form
2713693 Virtuoso exits unexpectedly when downloading from the cloud
2713295 leHiModifyCorner() fails when using partial selection mode in IC6.1.8 ISR27
2713242 Do not print UNIFIED_DB_STITCHING_DISABLE to the runSimulation script
2713040 Virtuoso exits unexpectedly when writing to a read-only database
2712355 When Pin Accessibility Checker is run, DRC issues are caused by misaligned PR boundaries of standard cells.
2711630 Cross probing does not work when using cell's view name other than schematic
2711317 Running job in ADE-L distributed mode could cause data loss
2710635 Unable to obtain current measurement in AMS/ADE simulation where resistor has parameter series=3
2710104 Annotation Browser does not report hierarchical Check Against Source errors when Scope is set accordingly
2709896 spectremonitor fails on a FIPS computer
2709511 The endOfLineKeepOut and widthRanges are not flagging violations for some widths
2709265 Schematic flatten splitting bus bits incorrectly
2709263 Schematic flatten causing extraction width mismatch errors for bus bits of a vector instance
2709205 Update the SKILL syntax for internal SKILL API
2708818 Area Estimator prioritizes PR boundary instead of bounding box for calculating area of sub-master cell.
2708773 Virtuoso fails unexpectedly while waiting for the license to be checked out
2708511 Remove demarcation between the ravel options
2707892 The graphical stimulus file is missing after the netlist is recreated
2707731 The vds process is missing basic awv functions
2706897 Cannot move rows and columns within Modgens by a specific ruler distance
2706129 Save statements not generated in amsControlSpectre.scs when running an AMS DSPF post-simulation in LSCS mode
2706002 The netSet property in schematic is not added to the layout instance in Layout XL after Generate All from Source
2705751 Tcl error warning during Virtuoso Space-based Router route summary
2704870 Virtuoso exits unexpectedly when recoloring a standard cell
2704687 The 'vfibatch' command errors out for the EM-IR report in IC6.1.8 ISR27
2704608 The Pin Placer changes pin size unexpectedly when it is placed to 'Top Level Route' and the route is a path.
2704434 While stretching a wire with Keep Wires Connected option specified, the unselected wire ends are moving
2704298 UNL Netlister ignores the option 'Ignore netType property on schematic nets' in the AMS Netlister Options form
2703829 Virtual supply not getting printed
2703392 Virtuoso exits unexpectedly during hierarchical copy and the copied instances are pointing to older source library
2703067 Reliability report does not show all devices
2702980 Waveform axes are not scaled properly when there are signals with different ranges
2702344 Library Manager exits unexpectedly during hierarchical copy
2702333 Calculator stops responding and reports evaluation error after a few net selections in the schematic
2702210 Virtuoso exits unexpectedly when the updateStatus command is run for a reliability simulation
2701979 The Auto-Create Pins command fails to open user interface as invalid layer purpose name is specified.
2701489 Virtuoso exits unexpectedly when rerunning unfinished points for a saved history
2701318 Auto via fails to create the correct via for specific combinations of metal widths
2700038 auCdl prints duplicated "m" when the lower-level instance param is defined as pPar(‘m’)
2699960 Virtuoso exits unexpectedly when running ADE Verifier
2699744 In Monte Carlo simulation, partial points will keep showing 'netlist finished'; they should show 'eval error'
2699655 Constraint database modification failed: could not transfer constraint because of an OA error
2698665 Attempt to change library references fails and Virtuoso exits unexpectedly
2696377 Abstract Generator exits unexpectedly on clicking 'Generate Abstract' option.
2695546 Reliability Report view shows the 'Disabled' status for a stress simulation using AgeMOS with URI model
2695481 Resizing issue occurs when switching between views in the EAD Browser
2694749 Unable to create wirebond at proper Z dimension
2694454 Area estimator calculates incorrect area when the design has a stack device.
2693368 The maximum intercepts of horizontal and vertical markers should consider only visible waveforms
2692932 Mismatch ID configuration (mc.yaml) is not captured within Open Debug Environment
2692549 Stimuli are missing from a recreated netlist
2690960 BGA lost in translation when Virtuoso MultiTech import is used
2690711 Digital signals plotted after an AMS simulation from ADE Assembler cannot be drag-and-dropped and reordered
2689863 Clicking the Apply button the Dependent Axis Properties form reverts the changes made to the General or Scale tab
2688265 Cannot create dataset when using default dataset naming with environment variables saveResDir, saveDir, and storeRelativePaths
2688246 The Auto-Create Pins command displays a message in CIW when the form fails to open.
2687915 Assisted Export does not delete shapes that have the FIXED_PRIVATE property
2687420 AMS UNL netlisting does not work on using sprintf(nil %s var) inside design variables
2686990 Allow download of simulation data for all corners of a cloud simulation
2686292 When the .cdsinit file and ADE GUI are used to specify -f, -F, -incdir, -v, and -y, output of the ocean script varies
2684390 Improve calcVal checks to report unbound variables
2683651 Filtering in the Run Preview tab of ADE Assembler is slow
2683410 Syntax error in the netlist when Spectre netlist when ignoreDesignChangesDuringRun is set to t
2683168 A saved AMS connect rules setup is not reloaded properly in a maestro view
2679572 The Violation Checks menu removes markers created by HCL Check from Annotation Browser while HCL Check retains markers
2679448 LEF In translation files because LEF58_TRIMSHAPE property is not supported
2678173 Issue with outdated design intent profile data when canceling the Edit DI form
2677037 Virtuoso fails unexpectedly while waiting for the license to be checked out
2676320 The Align command discards locked pins as a reference, when soft pins at level-1 are aligned to top-level IO pins.
2674939 Freeze Pcell Instance form fails to pick the correct destination master when the frozen master cell view is deleted
2673831 Virtuoso exits unexpectedly during Copy Library
2672986 Remove implicit nets if the related expression outputs are removed
2671938 Comparison of a SiP file against an OpenAccess layout fails if the SiP file is wrapped
2669998 XStream Out exits unexpectedly when using 'viaCutArefThreshold' with one row or column in multi-cut via
2669966 Improve calcVal messages to report design point and corner number instead of point number
2669636 Enable the Save button when run mode is changed
2666322 XStream Out exits unexpectedly when using 'viaCutArefThreshold' with one row or column in multi-cut via
2663874 In IC6.1.8 ISR25, Virtuoso exits unexpectedly when referencing dbSetAnyInstMaster
2646682 The libraries created by using the vmtcsvCreateComponentCellViewsFromCsv function causing issues in Assisted Import
2645640 IPVS run reports a false syntax issue for a dfm_property check
2644196 Unable to read metadata from violations database
2637662 Virtuoso stops responding due to an endless poll loop without timeout with MATLAB expressions
2636453 Some assign statements are not listed when the environment variable hnlEnableDriverLoadBasedShortRule is set to t
2620585 Filtering of corner sweep variables in Detail-Transpose view is broken
2620159 The MTS options form takes time to open and consumes 25GB memory
2616296 Cannot plot thermal waveforms correctly when using the 'Plot Signal from All Open DBs'
2614972 The sigtype=nil option in the 'Save By Subckt' tab of the Save Options form does not work properly after IC6.1.8 ISR10
2611947 Parameters 'fixedW' and 'fixedAR' cannot be set at the same time for certain lower nodes in the APR flow
2584231 cdsfrb_sge process never exits after simulation completes
2555346 Implicit signal still in the Output Setup tab even though there are no outputs expressions using this signal
2531905 How to set nettype=EEnet in the Interface Element (IE) Setup form
2524689 Enhance the Interface Element (IE) Setup form to support the nettype parameter
2483172 Spec Markers are not seen after executing the Swap Sweep Var command
2461534 Spectre AMS Designer Interface Element (IE) GUI must provide a way to set up EEnet connect modules or custom UDNs
2456934 Design Intent sign-off mark not working properly
2426489 Unable to get the target run result value with calcVal
2359255 Add a caution message to the Download All command to display the total data to be downloaded and seek confirmation to continue
2059500 Support EEnet or UDN connect modules with AMS in Virtuoso ADE
1815529 Configure bottom and top layers of a tandem or coaxial shielding constraint

December 2022

2758141 Tags are not retained when corners are moved
2756190 Using diffstbprobe at a sub-block during stability analysis gives a netlisting error
2755697 Checking out a schematic view and canceling the action makes a design managed maestro cellview read-only
2755363 The x_sides default argument of leModifyCorner is not applicable starting from IC6.1.8 ISR27
2754780 Wrong LPP chosen for the creation of VDR marker when voltage is negative
2748741 Virtuoso ADE errors out with SPECTRE-16850 message while running a stability analysis
2748446 diffstbprobe does not get netlisted correctly when probed at a lower level and errors out with SPECTRE-16850 message
2747594 Opening a schematic in edit mode takes more time than expected
2746842 diffstbprobe does not get netlisted correctly when probed at a lower level
2746503 OCEAN measure for Measure Across All does not work from IC6.1.8 ISR24
2746473 Signals that can be plotted from Results Browser cannot be plotted from ADE Assembler
2744452 Assisted flow breaks when concatenating SIPOA_TLINE properties and misses a blank
2743372 Netlist error when user-defined variables are imported from ADE L to a maestro cellview
2743210 MAS calculations get an eval error for both corners
2743054 The 'Plot/print vs' argument is unavailable even when the 'Number of occurrences' is set to 'multiple' in the 'delay' function
2741825 In the Virtuoso Automated Placement and Routing flow, removing an analog guard ring must restore the Modgen
2741027 Maestro cellview using multiple DSPF views gets stuck in netlisting phase
2740708 minEndOfLineSpacing and widthRanges give false endToEndSpacing spacing violations
2740342 Unable to change the spacing after dropping vias when Create Bus command restarts from an existing bus
2740257 High Current design intent push-up does not work if pre-existing top design intent does not have all its members defined
2740218 Include the transient dynamic parameter statement to the Spectre netlist generated by Virtuoso ADE
2739823 A design managed maestro view automatically changes to read-only when the check-in status of schematic or symbol views is changed
2739748 Virtuoso Space-based Router is not honoring maxLength routing constraint for M1
2739393 Reliability analysis in an AMS simulation returns an error when a variable is used for Temperature in age analysis
2739127 Reliability analysis in an AMS simulation gets stuck in netlisting phase due to a SKILL error
2739049 Virtuoso needs a few minutes to open a customer-specific maestro view
2737700 Simulation remains incomplete because some points get stuck in netlisting
2737112 Simulation in ADE Explorer is slow when Optimize Single Point Run and ignoreDesignChangesDuringRun are enabled and a third-party simulator is used
2736915 Check in of a schematic cellview makes a design managed maestro cellview read-only
2735786 An error occurs when plotting a BER curve for an eye diagram
2735511 Netlisting fails with errors for one maestro test but completes successfully for other tests
2735426 Stimuli Assignment form does not find variables defined in Vsources
2735371 Innovus produces a core file when trying to restore an MSOA design
2735273 maesimserv process cannot be launched on SUSE Linux Enterprise Server
2735235 Quick Align with Copy reference does not copy all preselected source objects
2735131 Within a Virtual Hierarchy, instances do not snap to a row region
2733721 Simulation remains incomplete because some points get stuck in netlisting
2733131 The 'Save By Subckt Instances' table does not save new entries in ADE Assembler, works fine in ADE Explorer
2731726 Custom calculator function not running correctly in LSCS
2731671 The openResults function returns an incorrect output when run from an expression evaluator process
2731626 Value for the Preset Override field is not set correctly when spectreXPresetOverride is set to customized
2730582 Row-based placement does not place standard cells due to the presence of markers
2730459 SKILL functions for changing the background color of Waveform windows shall be made public
2729717 Quick Align with Copy reference does not work on the first attempt
2729553 Batch mode process is not killed when the job is run in LSCS mode
2729383 The new value set for a local scoped option does not get updated in the netlist
2729236 Tooltip is not correct for the function YP in the Expression Builder
2729137 While specifying a path using design variables, expand the variable before specifying the path to the working directory
2728939 Assisted Export seems to drop SIPOA_TLINE property for some Pcell instances
2728331 Virtuoso exits unexpectedly when handling event filters
2727624 ADE Assembler does not refresh the Outputs Setup tab
2727127 Virtuoso ElectroMagnetic-EMX: EM extracted view fails with top-level selection
2726375 Custom parasitic parameters specified in the Semino section are not considered correctly for SmartView netlisting
2725119 Issue when using VAR in the model section for dependent variable
2724998 The values in the Dynamic Parameter table are retained even when all the rows are deleted
2724963 The VCP TAP Insertion flow and row creation are not consistent within a Virtuoso session
2724448 DEVICE_TYPE CDF parameter value from instance should be honored for compDef use
2724410 ciDiReplaceOrAddPropertyGroupDef fails as design intent profiles are not loaded during Virtuoso startup
2724247 Display proper errors when wrong DUTs are selected
2724137 Trunk Generation is not working when multiple local WSP regions exist and the routing area is PRboundary
2723543 PAM4 level 0 histogram cannot be evaluated in ADE outputs
2723401 Improve the error message for the netlist error received from a node entry for pnoise analysis
2722395 Extraction errors after flatten command due to disconnect between the no conn symbol and wire segment
2722012 Virtuoso stops unexpectedly after frequent right clicks in the Corners Setup form
2721484 diffstbprobe does not get netlisted correctly when probed at a lower level
2721378 Contents of the graph labels cannot be copied and pasted using the RMB options
2721219 CDL netlister does not honor lxRemoveDevice property on vdc when vdc is connected to iterated instance
2721216 CDL netlister does not honor lxRemoveDevice property on iprobe when iprobe is connected to subckts
2721215 CDL netlister does not honor lxRemoveDevice property on diffstbprobe when diffstbprobe is connected to subckts
2720860 Virtuoso stops responding and Window Manager freezes after the global variables with config sweeps are dragged and dropped from active setup to run plan
2720616 ciCacheGet(cv) models return nil when setting envSet 'conTypesOnDemand'
2719834 Netlisting must report errors for removed or renamed nport instances with S-parameter cell specification
2719662 Unable to run Spectre EMIR analysis from an OCEAN XL saved from Virtuoso ADE
2719407 Netlist syntax error is reported during fault generation
2718442 AMS UNL netlisting error in an AMS simulation run from a maestro cellview
2718126 Extract the desired signal from AC psf database
2718076 Auto Generator Hierarchy is enhanced to reuse cell methodology for custom cells
2717993 SKILL Lint rule for pcDefinePCell incorrectly informs about a global variable in the default parameter expression
2717840 Check in of a design managed schematic cellview incorrectly tries to make a maestro cellview read-only
2716018 Net Tracer warning message displayed regarding the attempt to create a layer
2715531 Wrong LPP chosen for the creation of VDR marker when voltage is negative
2715313 The Insert Filler Cells command does not respect the cellname filter specified in the row template
2714802 The Map Bus Name does not replace <> to []" when hnlMapNetInName is set in simrc
2714610 User-defined macros differ due to antenna diode related ground pin in a design
2714562 SpiceIn does not update port direction with pre-existing symbol when the Overwrite cellviews option is set to ALL
2713404 check_single_shape needs to gather sameMetalAlignedCut violations
2713171 Create new dataset causes existing datasets to be disabled
2712043 Incorrect related power pin extraction by Virtuoso Power Manager
2711344 Warning message displayed that techCreateLayer layer number 1150 already exists when adding a net trace
2708948 Remove the limit of 10K points in a single fault simulation run
2708663 Issue in isolation_enable_condition derivation utility
2708499 SiP-Design Rile Check (DRC) flow should not have dependency on the order of Virtuoso and SPB tools in the PATH environment variable
2706430 AutoVia is leading to sameMetalAlignedCuts violation
2706389 Netlist error is reported after the hierarchical copy of a library with a smart view
2706053 Error messages are reported when closing the layout window
2705719 Remove hspice view for rcwireload component in the Analog Library
2703677 Plot across Corners and Plot All not working for parameterized getAsciiWave
2698182 Router having issues with 3 and 4 terminal bus structures
2697590 Object layer-purpose pairs incorrectly removed from the Layers palette
2694797 Results of nested sweep pss-fd cannot be plotted in Virtuoso Visualization and Analysis XL using Calculator
2692670 Renaming or copying an EMX library does not complete the command successfully.
2692666 Results are not plotted in Virtuoso Visualization and Analysis XL using Calculator, but are plotted fine in the Results Browser
2688023 Renaming or copying an EMX library does not complete the command successfully
2684369 Neither upfront error checking nor calcVal lint check the correctness of the ?result argument
2683848 User-defined macros differ due to the pg function in a design
2683846 User-defined macros differ due to antenna diode related power pin in a design
2682917 Incorrect sorting of Pass/Fail values
2681402 VALE schematic migration: Schematic with off grid wiring created short on migrated schematic
2677663 DRD functionality does not recognize some of the layers listed in layout
2677457 The Link Graph feature does not work as expected when multiple axes limits are set manually
2677449 The Link Graph feature does not work as expected when multiple axes limits are set manually
2677436 The Link Graph feature does not work as expected when multiple axes limits are set manually
2677429 The Link Graph feature does not work as expected when multiple axes limits are set manually
2674226 Cannot process batch runs in parallel with implementation sets
2672998 AMS UNL netlisting issue due to a missing presistor instance
2662923 Users need to restart Virtuoso to make the eye diagram work
2648166 Area Estimator is enhanced to support i1278 flextor schematic Pcell
2627515 An incorrect error message is shown when corners are enabled in the run plan but disabled in Data View
2610969 VDR labels with different values created on same layer
2608305 Using VAR syntax in noise circle expression gives an error in ADE Assembler, works fine in ADE Explorer
2602408 LSCS job remains pending indefinitely for post-layout simulations across corners and certain output expressions
2600449 Renaming or copying an EMX library does not complete the command successfully
2578976 Changing the 'Common reference' setting in Property Editor form does not work as expected
2568872 Cannot change Stage pulldown to show stress simulation in Reliability Report view for age+she
2557411 Voltus-Fi: Violation Browser option is repeatedly selected and deselected and Virtuoso stops responding
2542276 Virtuoso stops unexpectedly while specifying Checks/Asserts options
2518102 Selecting one Max Resistance highlights all other Max Resistance paths in schematic
2481205 maeSetVar does not work for local variables when the current value is a sweep set
2477035 Design variable is not seen in Design Variables field in ADE Explorer after importing setup
2336033 Data View/Setup Assistant shows overridden errpreset for Spectre X, APS, and Spectre, misleading users
2009590 Virtuoso Visualization and Analysis XL exits unexpectedly when running simulations
1485721 The Running step Abstract form does not display the Overlap and Grid tabs

February 2023

2778577 Area Estimator throws parameter warning while estimating the area for the specified schematic
2772025 VerilogIn issues OpenSSL internal error on a FIPS-enabled machine
2768789 Aging simulations remains in pending state
2768317 Switch_pin not extracted correctly
2768052 FigGroup containing a multipart path and a pin is flattened when copied from one cellview to another
2767148 For minEndOfLineSpacing constraint, DRD flagging sameMask constraint violation for a diffMask
2766560 Abstract Generator exits unexpectedly because the Power Rails Analysis message exceeds the character limit imposed on the strings
2766080 Netlisting fails for Verilog-AMS cell that has 3 million pins
2765395 Spectre Monitor is not terminated and remains idle after exiting ADE Assembler
2764794 diffstbprobel_gnd netlists with incorrect probe syntax causes simulation errors
2763983 The Stress option is not available to select from the Stage drop-down list in the Reliability Report view
2763262 diffstbprobel_gnd netlists with incorrect probe syntax causes simulation errors
2762314 EAD LTE does not generate correct power values in Power Instance File for dummy devices in the child cell
2762172 Concurrent Layout fails to refresh data with SOS cache mode
2761760 When the Snap wires to snap pattern option is set but there is no WSP, the Create Bus command uses minSpacing
2761758 Virtuoso exits unexpectedly during an implementation run in Virtuoso ADE Verifier
2761394 Using Static EMIR analysis generates wrong statements
2760621 History results get overwritten when other histories are merged in it
2760437 Spectre monitor stays on the grid and uses 100% CPU after a simulation is stopped abruptly
2760422 The simulator log file is missing in a Monte Carlo simulation
2760377 Unable to read vertical marker information
2760000 Suspending jobs from command line and stopping them in GUI starts launching undesired simulation jobs
2759923 Create correct 45-degree slot edges when slotting 45-degree path segments
2759455 EMIR Analysis with SHE for a specific foundry performs unnecessary checks
2759452 LTE power file must check multiplier value and distribute power accordingly
2759185 Simulation fails when suspended LSCS jobs are restarted in ADE Assembler
2758926 Coloring conflict occurs in the Pin Accessibility Checker when uncolored extended pin view is used by the router
2758686 An error occurs when running stability analysis with diffstbprobel_gnd
2758500 Running an AMS simulation in ADE Explorer gives the error 'sh: cdsDiff: command not found' in the terminal
2757556 FuSa report cannot be generated
2757421 Results tab does not display the updated values when alternate data sets are loaded
2757102 Avoid message boxes when running simulations from ADE Verifier in non-GUI mode
2756835 Spectre output displays unnecessary device information due to the wrong netlisting of the DC option 'where'
2756814 Virtuoso exits unexpectedly when batch mode simulation is stopped using the Stop button on the main toolbar
2756763 Using AMS UNL with ADE Explorer gives the error 'sh: cdsDiff: command not found'
2755379 Exclude Types setting does not work appropriately for the Routability Check command when invoked from the Wire Assistant
2755038 Wire Editing with allowedJogWidths creates jogs with wrong mask color
2754238 Virtuoso exits unexpectedly when recreating a Pcell
2753874 In ICRP mode, the calcVal function in the Monte Carlo simulation pulls a value from an incorrect point
2753067 Error occurs during AMS reliability simulation when using the Configure Stress File option
2752756 When running the FGR chop command, the Contact Space value resets to a different value in latest Virtuoso version versus IC6.1.8 ISR16
2752636 Virtuoso stops unexpectedly when running a run plan
2751961 Cannot open the Axis Properties form for y axis again after changing the axis properties in a certain way
2750903 Virtuoso Power Manager could not run due to issue in UPF syntax
2750781 In some cases, LSCS does not show all the commands in the context-sensitive menu to view log files
2749554 If a cell name of a testbench starts with a numeric character, the waveform is not plotted
2749549 An analog2digital expression sent to ADE Assembler returns incorrect results
2749406 The Auto-Create Pins tool failed to create pins for the specified net shapes when run in Schematic Aware mode
2749364 Virtuoso exits unexpectedly when flipping objects with a large number of vertices in a layout
2749317 Symbol compression fails after adjustment
2749205 Wrong parameter calculation of FGR in latest Virtuoso version versus IC6.1.8 ISR16.
2749198 The View Implementation command in Virtuoso ADE Verifier does not work for remote or batch runs with LSF
2749008 Virtuoso exits unexpectedly when extracting a layout with a non-uniquified module hierarchy
2748480 Noise separation not working with selected instances
2747944 The Monte Carlo setup form does not accept dumpseed as an additional option in the Netlist Options field
2747890 Need an environment variable to globally disable quick plot data
2747806 Need an environment variable to disable quick plot data for all implementation used in Virtuoso ADE Verifier
2747564 Number of points submitted for simulation do not match the points selected in Run Preview
2747420 Passing pPar for model of analogLib cap causes OSSHNL-305 conflict error in AMS UNL netlister
2747346 Netlist creation fails in LSCS when a ternary conditional operator is used to set the temperature
2746344 The TDDB result view is disabled when using the LSCS method for job distribution
2744493 Saving the symbol view causes Virtuoso to become unresponsive
2743667 Models from the ahdlLib and rfLib libraries report errors when amsLibCompile is used
2743236 Virtuoso exits unexpectedly when dbSave() is applied to Virtuoso Layout Editor
2741895 Cannot set reference edge for quick align inside preselected instances with an overlapping text drawing rectangle
2741419 When using a transient dynamic parameter, a previously removed design variable reappears
2741189 A bus created with analog2digital using awvCreateBus has an incorrect expression when sent to ADE Assembler
2740308 The Quick Plot command does not plot all waveforms
2740008 Checker shows the wrong minEndOfLineSpacing reference when multiple rules are specified
2739509 Cannot plot graphs for stress simulation when the Save Intermediate Results option is set to either None or Some
2738775 List of instance IDs not passed to vcpfeRegisterPostPlacementProc when boundary=rowRegion
2738710 Scaling is not effective for HPR metal extraction
2737643 Batch checker reports pin spacing violation due to NetClass spacings similar to IC6.1.7
2737394 ADE Explorer does not generate correct netlist with postlpreset and postlnets using Constraint Manager
2737074 Incorrect netlist is generated for Verilog-A views when hnlUseSchematicForInherittedConnection is enabled in the. simrc file
2736966 ADE Verifier is creating more jobs than the max limit when implementation runs are started incrementally
2736853 DEF Out cannot export information related to ROUTEHALO
2736568 Save signal statement is missing in the netlist when running simulation with the config view in EAD
2735316 Isolation modeling issue
2734753 Support generic parser in the custom self-heating effects (SHE) flow
2734410 A disabled tcl file is lost after saving a maestro view or running a simulation
2732409 Incorrect netlist generated when using the 'Generate noise' option with mtline analog library model
2730456 Not able to edit points of cutting boundary in the GUI
2728990 Abstract Generator does not work as expected in ICADVM20.1 ISR28 during power rail analysis due to segmentation fault error
2728760 Cannot save signals with the selected mode when the design with a period in the library name is simulated
2728317 Cannot select the desired edge as the reference for quick align when another overlapping edge is present
2727130 Simulation schematic generation incorrect when ports are overlapping
2725823 Feedback loop issue
2725108 Unable to complete a DRC clean route with a single horizontal M1 wire between the two pins and involves additional routing layers
2723970 Cannot plot the S-parameters when the specified mode for S-parameter analysis is 'other'
2722420 Auto P&R fill is leaving gaps and moving devices
2721251 Abstract Generator exits unexpectedly in the abstract step during power rail analysis
2720085 abeLayerAvoid produces incorrect results
2719728 Pin size and layer changed for Pcell instances after assisted export
2719721 A bus created with analog2digital using awvCreateBus has an incorrect expression when sent to ADE Assembler
2719456 The View Netlist command in the context-sensitive menu of results is not enabled for a fault simulation
2718009 Library import could not be completed
2717594 In Virtuoso ADE Verifier reference flow, simulation run reports an error when the parent requirement is editable, but the child is non-editable
2717270 The selection mechanism of the Pin Tool user interface needs to be enhanced for better usability
2715840 calcVal arguments ?cornerName and ?matchParams are not working correctly together
2715648 The ?ignoreParams argument of calcVal set to rest interferes with a Monte Carlo simulation
2715371 Unable to infer antenna diode related power pin for flat and user-defined macros
2714607 User-defined macro differs in a design by voltage_name
2714604 User-defined macro differs in a design by direction
2714601 User-defined macro differs in a design by pg_type
2714599 User-defined macro differs in a design by power_down_function
2714595 User-defined macro differs in a design by related power pin
2714453 Via Property Editor displays the wrong metal layer for backside BV0 via
2706619 Calibration over corners fails due to brackets around calcVal expression
2697957 The waveform icon appears in results although the expression has an error
2691288 Load markNetOptions from a base technology file when the ITDB technology file references the base technology file
2683849 User-defined macro differs in a design by switch function
2674873 Getting an xmelab RNGDIR error on using the simrc variable simVerilogBusJustificationStr or hnlSetBusDirectionDescending
2669632 Using the View Results shortcut command for an implementation opens the maestro cellview in modified state and shows the Save prompt when the cellview is closed
2665041 Need read-only histories to come along when a maestro view is copied
2648334 Virtuoso keeps exiting unexpectedly when doing various layout tasks such as moving objects and editing cells in place
2643096 Improper connectivity handling when modifying a pathSeg in Layout EXL with EAD Browser active
2642126 Clean up the relationship between the ?matchParams and ?cornerName arguments of calcVal
2632551 Verilog Netlister generates an incorrect netlist when multi-dimensional buses are used in the schematic
2632171 Net tracer traces a net from package down to IC but cannot trace it back up to the package
2631266 The Library Property Editor form is displayed behind the Library Manager in RHEL 7.9
2622318 Metal short resistor Pcell - Need to twice generate as schematic for Pcell to get evaluated correctly
2615346 GUI does not reflect what is netlisted when using pnoise sampled if Change is not clicked
2598190 Image export operation removes some layers
2590166 Virtuoso SystemVerilog Netlister creates an incompatible netlist that fails when running simulation
2590108 pnoise sampled fails when not clicking Change after Enable/disable on Choose Analysis form
2576818 Impedance plots are not correctly plotted when loading a graph window from a .grf file
2551832 In the referenced flow, changes made in maestro views are updated correctly in referenced cellviews using AutoSync, but not propagated to the top Verifier cellview
2520514 After the Re-run Unfinished Points command is used in LSCS mode, the context-sensitive menu of results is like ICRP
2498198 The maestro cellview setup disappears after a run plan run is stopped by lint checks
2494147 An analog2digital expression sent to ADE Assembler returns incorrect results
2472344 When Area estimator is run and the design contains iterated instances, the iterated instances become scalarized and as a result the schematic is modified
2259631 Incorrect points are taken when specifying variables through the 'Add Specific Points' option for AC analysis
2182536 Using plotting template when there are no results to be plotted causes Virtuoso to exit unexpectedly
2162370 A bus created from analog2digital results in an incorrect expression when sent to ADE Assembler
2155201 The Save a Copy command does not work for read-only histories in ADE Assembler
2046842 Provide better ways to access the Spectre log for a fault simulation
2043783 Provide better ways to access netlist, job log, and Spectre output for a fault simulation
1888640 The Save a Copy command does not work for read-only histories in ADE Assembler
1778962 Any change to the Resolution field in the Save Image form is not honored

March 2023

Base_ICADVM20.10.000_lnx86
Hotfix_ICADVM20.10.210_lnx86
Hotfix_ICADVM20.10.220_lnx86
Hotfix_ICADVM20.10.230_lnx86
Hotfix_ICADVM20.10.240_lnx86
Hotfix_ICADVM20.10.260_lnx86
Hotfix_ICADVM20.10.280_lnx86
Hotfix_ICADVM20.10.290_lnx86
Hotfix_ICADVM20.10.300_lnx86
Hotfix_ICADVM20.10.310_lnx86