Cadence SSV Release Version 22.11.100
Cadence SSV Release Version 22.11.100 | 23.6 Gb
The SSV Release Team has unveiled the Cadence Silicon Signoff and Verification (SSV) 22.10.000. This solution encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout.
Featured Enhancements
Here is a list of some of the important updates made to Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution for the 22.1 production release:
Tempus
Aging-Aware STA Analysis
Semiconductor device performance degrades over time due to various physical phenomena, such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and process node/device failures. The major factors responsible for device degradation are stress duration, temperature, supply voltage, and logic conditions. Traditionally, timing margins are used for accounting for aging-related timing degradation. The Tempus advanced aging-aware timing analysis addresses aging-related effects accurately, minimizes margins, and improves the PPA (power, performance, and area) of a design.
Inter Power Domain (IPD) Analysis
An increase in the number of power domains in a design has become a challenging aspect for designers. This has resulted in a significant increase in the number of timing signoff corners due to cross combinations of voltage corners. This also leads to long cycle times and large compute requirements for timing signoff. To reduce the cycle time and computation requirements, Tempus provides the new capability to run inter-power domain (IPD) analysis, where only IPD logic in the design will be analyzed, and the timing reports will generate data for the relevant IPD logic only. The reduced capacity requirement per IPD run helps to analyze the IPD logic of the design efficiently.
Via Variation Flow
The statistical via variation feature allows you to define the sensitivity of via resistance as a function of area. Tempus computes the interconnect variation based on statistical via resistance. To support the via variation flow, additional data for modeling via variation is required. This includes via variation side file that contains look-up tables of via resistance statistical data and the extend SPEF file that contains via resistance layer and area information. Tempus timing reports show interconnect variation in the results when via variation is enabled.
Voltus
Performance and Capacity Enhancements
The following enhancements have been made to increase the performance and capacity and provide a better user experience for large designs:
- Support for localized disk data caching to retrieve information quickly and speed up the processing time
- Enhanced capacity for die-model generation by using the advanced Model Order Reduction (MOR) techniques
- Improved the method for fracturing Non-Manhattan shapes, enabling current-aware modeling of the shapes
- Enhanced algorithm for hierarchical net-tracing in designs with many hierarchies
Simplified Use Model for Power Analysis Flows
A new seamless unified solution, "Event-Based Power Analysis," has been introduced to support multiple power analysis flows simultaneously. In this model, the tool performs accurate state-based power estimation for all events of a scenario in a design. Event-Based Power Analysis is applicable to all event-based vectors, such as VCD, FSDB, SHM, and PHY. The use model for event-based power analysis is: set_power_analysis_mode -method event_based.
New Smart Windows Feature
Voltus introduces the new smart window feature for extracting peak power scenarios from a vector-based activity file. The smart window is a variable size window that enables designers to capture maximum regions of high power dissipation.
Support for Multi-Die Self-Heating Effect Flow
Voltus now supports the multi-die Self-Heating Effect (SHE) analysis flow to understand the effect of temperature variations in gate-level designs. Previously, the SHE flow was supported only in the single-die mode using the analyze_self_heat command.
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Fixed CCRs in Tempus 22.10 RTM
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2670028 Some designs error out in some cases
2663928 Cpl on a bidi net goes away when bus_attacker_accuracy_mode 4 or estimate_glitch_method 3 are used
2663817 Library loading errors out while reading and merging aging libraries
2661926 get_property does not return timing point name in DSTA
2657163 save_design does not create link of libs compressed in .gz format, while saving db in DSTA CUI and LUI flows
2651587 DSTA not recognizing variable inside get_db
2644953 High transition values reported in ETM library generation
2644534 IPD) High scope size in bounded corner run (SMMC with max min corner) is not bounded in max corner (SMSC run)
2643424 Tempus has inconsistent handling/merging of single-edge clocks at multi-input gate
2642725 Context beta feature is required in DSTA - but not STA
2641606 Incorrect reports with null clock/garbage nets for report_noise -style detailed in DSTA-CUI
2641484 Large negative delay on through pad
2632814 Separate EM/corner library add to base timing/corner library
2632738 SEGV in report_noise -sort_by slack -gui_victim_nets_file
2631026 Generate SDF similar to SDF generated without retain data in some cases
2630663 Make set_si_mode -eco_accuracy_mode 1 default
2627060 DSTA CUI - proper message to be provided in case of no machine available
2626374 Stack trace during CCS-TN noise Liberty model only
2625755 report_timing -retime_max_slack does not report paths unless -max_slack is >= PBA slack
2624938 ERROR: (TA-1029) *DIAG:(Missing Adj)
2624435 Improve Tempus heuristic for inferring voltage/temp when exact match is not found
2624431 Tempus binds set_driving_cell library to wrong voltage in some designs
2623926 update_timing -full errors out
2613954 Report fields are getting merged together instead of having spaces between them
2612035 Stack trace with set_annotated_delay -cell
2611688 Voltage interpolation when one of the voltages is constant
2609725 Errors during check_timing -verbose -tcl_list
2609372 Tempus errors out during set_delay_cal_mode -use_diff_volt_in_eiv_timing_analysis run
2606690 Add newNetname option to the addRepeater command
2605711 report_noise writes out .rn files in the local directory
2604167 Huge memory used when reading libraries
2603096 API tomIsCteDelaysUpdated returning false for a STA client saved with update_glitch
2601503 Package Paradime improvement settings or make default
2598796 When Paradime client errors out, the status of the other clients be placed into the log file
2598761 **ERROR: (SCOPE-2493): Error in writing consistency data
2598251 Syntax error TA-120 while reading SDF
2597097 Tempus errors out after merge_timing_reports command run
2592491 set_clock_exclusivity for generated clocks of same master clock at output of Mux
2592420 Voltus errors out at handling SDC with segmentation fault core dump
2592091 Enhance write_ldb to eliminate check on TECHLIB-1277 WARN to generate LDB file
2591797 ROP calculation is affected by change of reporting thresholds from set_glitch_threshold
2590441 Errors due to index not found
2588222 Tempus errors out on report_timing -retime
2587394 Request for new property for borrow-edge-adjust - is_borrow_edge_adjust
2582167 get_db attributes do not provide information in DSTA
2580297 Uniquify the empty module names so that they do not collide across boundary models
2579608 update_glitch errors out with LC
2579558 report_noise errors out with LC and many attackers as well as boundary model
2577611 Valus is issuing TECHLIB-1445 even when state_function or statetable is present
2574836 SLBBV to come to the same order of analysis views when same libraries are read
2574000 Tempus errors out while restoring the design
2572257 Issue a warning message when boundary model is read from a different version
2565483 CPPR calculation difference between versions
2565443 CCR to track the documentation of all DSTA error messages reporting in master log
2565433 Boundary model to give proper warning, if there is a problem during creation
2564854 "set_db timing_report_enable_cppr_point true" or "-debug cppr_point" does not work for Stylus format report_timing
2563803 Tempus errors out for several hours after "reset_clock"
2561103 Tempus consumes excessive memory and does not release it during do_extract_model
2560448 CTE runtime hit during update_glitch
2560173 DSTA-CUI: Tempus errors out while saving the design post distribute_partition
2558822 High runtime during outside partition marking
2558794 read_spef to give error, if boundary model SPEF is deleted between set_top_module and read_spef
2558194 Long runtime due to clock nets with fanout > 1000
2554489 Change default limit of 100s for Valus to catch big numbers in .lib
2553709 Request a warning message any time the RIP > VDD
2553705 Support an option for Tempus to exit if the boundary model is deleted while Tempus is running
2552565 report_noise to write temp files to TMPDIR instead of local directory
2551843 Ignore endpoints to modules with missing libraries when creating a boundary model and issue a warning
2551615 Different vdd's leading to large area/width
2550226 N3 base delay has outlier during voltage extrapolation
2548951 Add an option in read_boundary_model to skip endpoint tracing for empty modules
2548864 Provide a way to skip net(s) from being loaded from the boundary model
2548810 List each boundary model as it is being read in
2548214 Errors when using testcase with boundary model
2547805 Stack trace while generating annotation summary
2547527 Several hours runtime for report_annotated_delay, after read_sdf with 16 threads
2547471 Tempus PBA result is worse than GBA result
2547099 Document list_libraries "-used" and "-used_analysis" options
2545266 DSTA CUI: Tempus saves original Verilog netlist path instead of IMEX::dataVar while saving design
2542765 DSTA CUI: Tempus does not dump relative library path or path absolute to design DB saved by write_db
2541680 Provide a metric in log file, such as runtime histogram, for understanding runtime
2541679 Make set_delay_cal_mode -eng_bugFixLC true default
2541026 Errors in update_glitch
2539792 Add Tempus ECO xtalk and glitch support over cell-edge + net-edge, i.e., delta_delay_annotation_mode arc
2539780 Remove spaces between libraries in custom glitch report
2539778 Issue a warning message when area or width are large
2539176 DSTA CUI: Getting DPO as result on querying name of rc_corner
2538203 Ensure there is a space between values in glitch report
2536090 SDF errors TA-120 during report_annotated_delay after read_sdf
2535732 Merged ETM libs with different merging modes and having identical timing tables are printed separately
2535387 DSTA CUI errors out during report_clock_timing
2534780 Errors in update_glitch on full chip design
2532419 Unreasonable incremental delay for a net
2531750 Support an option to output TECHLIB messages for cells used in the design only
2528568 Some Tempus versions show CPPR point difference
2524933 Errors in some Tempus builds
2522303 Restore design, followed by update_library_set, context is not getting re-loaded
2520900 report_delay_calculation -si is not giving aggressor net information
2520752 Bus ATT less than IAT should be able to be set as quiet_attacker
2515667 Tempus ECO timing does not converge after ECOs implemented in Innovus
2515552 Fix for checking if define_bundled_bus nets are PG nets, does not work when Verilog uses n({VSS, VSS}) type syntax
2513616 Innovus errors out during SignoffOptDesign
2512355 DSTA CUI is returning some collection (get_db), even when pattern is not found
2512174 CUI command create_cell_signal_em_model errors out when using read_libs -max_libs
2511927 Errors in report_noise
2510741 Errors in infer_pgv_intent in some cases
2509066 Errors in create_glitch_boundary_model when testcase is missing DCAP lib
2507770 All sequentials are not all_registers
2507699 ETM generated is not capturing in2out path
2507398 DSTA exits with error "IMPTCM-48" while reading power content information from CPF
2506842 report_timing_derate does not report power domain based net derate, reports power domain based cell derate
2506429 Number of fields and headers should match in glitch report
2506423 IMPESI-3428 to check if net is PG net
2505449 Tempus errors out upon execution of "distribute_report_runtime" command
2501916 Area and width is merged together
2499964 Tempus/Innovus DB restore errors out when set_quiet_attacker references inactive analysis view
2499494 Add the total number of nets to the progress report
2498738 Errors in Paradime run in AAE
2498736 Errors in Paradime during report_bus_bundle with bus merging
2498734 Errors during Paradime run
2498197 Several timing path properties are not mapped in get_db, when compared with report_property
2497779 update_delay_corner -irdrop_data(file) does not annotate
2497389 Boundary model flow not working in CUI - exiting with error "I(MPIMEX-12): 'init_design' failed"
2496648 get_db mapping required for properties of report_noise -collection
2496236 Errors in report_noise
2496020 User-defined attributes issue in Tempus DSTA Stylus mode
2494459 report_noise -collection to include slack values
2493482 Add new message if net is PG net for IMPESI-3019 and IMPESI-3018 checks
2493423 Change nobus behavior with LC
2492802 DC Tol happening instead of ROP due to numerical instability
2491299 While fixing Hold in hold path group, Setup degrades in Tempus HC-ECO
2490585 Incorrect numbers showing up in glitch report
2488093 get_db analysis_view .is_active and all_analysis_view -type active shows different result in DSTA CUI mode
2488083 Tab option with get_db does not work in DSTA CUI mode
2487750 Voltage interpolation for Macros support
2487730 Need "create_property_alias" support in DSTA
2487545 Tempus Paradime errors out during eco_opt_design
2483288 report_noise -collection does not work if delay switch is specified
2483285 report_noise -collection does not work in DSTA CUI mode
2481249 set_delay_cal_mode -doonly {netnames} to issue a WARN if the net names are not valid
2481229 [get_db current_design] is not supported before distribute_partition
2480940 Add (Threshold) header back into ROP portion of glitch report when format option is specified
2480939 Verbose LC reporting is causing errors in glitch reporting
2480853 Support B: & ~B: in report for the net name
2480534 DSTA CUI: Command related information not dumped in client log file and commands not dumped in command log
2476232 Errors during report_timing -collection run
2474405 Bus bits that are connected to one instance only are not printed in bundle file
2471491 DMMMC master not exiting even though client jobs errored out
2470769 Errors at msvCheckSourceSinkDiffSupply() during commit_power_intent after read_design
2469618 eval_legacy {get_delay_cal_mode} is not working in distributed mode Stylus run
2469606 eval_legacy {get_si_mode} is not working in distributed mode Stylus run
2465137 Support for write_db -user_path
2464523 Incorrect reporting for early/late_clock/data_pg_net_voltages with IRDB annotation
2463559 report_timing_derate does not report timing derate of all power domains link/bind to specific delay corner
2462179 Wrong setup check time in Tempus client in signoffTimeDesign with IRDB
2461876 save_design errors out while running DSTA in Stylus mode
2461376 WARN: (IMPESI-3468): User needs to specify -equivalent_waveform_model propagation first before specifying -w
2461363 **WARN: (UI-338): Variable 'timing_enable_wire_load_model_support' is obsolete and has been replaced
2461130 Tempus not returning worst path
2461099 distribute_design_views to support the passing of the "invs" license with "-lic_startup_extra invs"
2459639 New attribute on generated clocks with all the pins from the master clock root
2459627 Switching capacitance in the glitch report needs to show the analysis switching capacitance
2459456 Delay Calculation first iteration run in constraint delay-corner update run on a restored session
2457981 Disable clock assertion after timing context is read to avoid errors
2457758 SPICE ground capacitance for the victim is larger than the SPEF ground cap
2457731 Add control for limiting how many busVAs are included in the simulation
2457460 report_timing_derate does not report derates of all power domains bind to delay corner, report_timing reports
2456551 Unexpected glitch violation
2456079 Check if bus bundle net is power/ground and issue a warning
2455899 ETM generation takes several hours in some cases
2455716 Combinational arc for a port not characterized in ETM
2455692 set_instance_library used but terminal voltage taken from PG net voltage assignment
2454240 current_design returns null value in Tempus STA run and reports error in DSTA run
2452946 SPICE deck with expand bus enabled should write out all the attackers
2452798 Incorrect minimum rise delay reported
2452596 Tempus errors out while echoing any variable in distributed mode
2450183 Report only ACT attackers in the glitch report
2449548 set_pll_timing changes the slew at output of PLL
2448484 report_noise -quiet_nets with set_quiet_aggressor -aggressor does not show small aggressors
2448377 Missing OCV on output pins
2448091 Request to verify all necessary files are present for glitch boundary model
2448088 Attacker state for busVA components needs to be reported with glitch properties
2447608 IMPESI-3194 seen in PGV Flow
2446345 Applying the boundary model constraints should not exit, if there is an error with one
2444002 PBA slack not bounded with GBA, when set_input_delay is used with reference_pin
2443172 Use Prp noise for estimated glitch when determining if glitch will be simulated or not in the 2nd iteration
2442861 High runtime with leakage ECO with low fix rate and .summary file not getting dumped
2441443 CPU HC ECO client errors out during delete_repeater
2440618 High retime slew for INV cell
2440312 apply_boundary_model_constraints does not accept a - in the bus bundle name
2439329 Flop with large timing difference between signoffTimeDesign with Tempus and Tempus-PI
2435053 When IMPESI-3345 is issued, the failure criteria should change from ROP to RIP
2434416 set_cdb_binding is not logged in the logv/cmd file
2434398 Larger than expected runtime increase of bus over nobus run
2433785 Tempus DSTA errors out due to large number of comments in SPEF file
2429552 Paths go unconstrained inconsistently in C-MMMC
2429475 Tempus eco_opt_design -power degrades setup time
2427620 report_noise should not print list of nets or pins in the glitch report
2427005 Request to add 'Function' attribute for Feedthrough Port
2420705 Support to override the UDN failure criteria
2417838 Show info message when reading in constraints from boundary model
2415896 lib_arc mode attribute should support multiple etm_modes per arc
2412082 Need CUI mapping for set_eco_opt_mode -add_inv_pair
2400573 Voltus and Innovus not aligned for check_connectivity options
2365392 Need CUI command/variable for set_si_mode -si_reselection_glitch_threshold
2364603 write_timing_model (do_extract_model) SEGV
2362411 ETM not generated with MT enable
2360565 Apply LC to bus bits in bus attacker
2356192 Dynamic net derate of 1.0 is not considered
2352669 Request to dump last net(s) analyzed when run appears to be low on memory
2321074 Generate correct stimuli file automatically when generating Spice netlist
2309966 CUI equivalent option of -include_used_subckt of create_spice_deck command
2308031 Differentiate GBA slacks based on nworst and max_paths for incomplete or leftover endpoints in EPBA timing report
2305098 Request to merge bus groups together from block boundaries during top level run
2301793 Invalid value 'enum' specified with '-retime' for 'report_chain'
2291399 Tempus voltage difference physical vs logical mode, read_design -mmmcFile -setup_views -hold_views -dynamic_view -leakage_view
2278476 Limit the number of attackers before bundling for the bus
2272364 Add local clock skew details to report_timing timing report
2262403 Need check_timing option to sort verbose report by check type and not pin
2260680 merge_timing_reports in CUI is dropping path header information
2232843 Need to support "get_pins ./<somepin>" relative to a current_instance
2198804 opt_signoff is not working in some cases
2191274 Correct the spelling of characterization in timing_extract_model_enable_context_independent_latch_thru_charaterization
2184670 Put WARN messages around UDN warnings and indicate which cell they belong to
2183961 Add the glitch type to the IMPESI-3205 message about small injected noise
2115237 set_clock_sense -negative not generating correct clock
2101199 Valus does not raise any warning/error message for negative and junk sigma timing check values
2089054 CPE and PM modes report incorrect state dependent leakage
2078022 Enhance Innovus to fix overshoot/undershoot violations
2028397 Report glitch analysis progress in the log file - to indicate run is progressing
2022874 Multiple options of check_legacy_design not working in Tempus Stylus
1786676 Incorrect error in Valus Liberty validation for missing 'timing_sense' attribute, even if 'timing_type' is already present
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Fixed CCRs in Voltus 22.10 RTM
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2677674 Voltus errors out during rail analysis
2674363 Voltus errors out during the simulation stage
2671531 VTM flow does not consider sub-block orientation for power map generation
2669921 Voltus errors out when running report_rail in the XP mode with report_power in parallel and 3rd party Extended SPEF
2667152 generate_pg_library fails to calculate the current distribution
2664326 CUI should support set_power_analysis_mode -auto_distribute -auto_distribute_threshold
2662172 validate_pg_library does not honor cell foreign
2657443 averagedump of TC_SUM is greater than the averagedump of the dynamic ptiavg file
2656542 CCS current increases with run time when using the CCS library for vectorless and state propagation
2656290 Voltus PGV generation fails flagging shorts between power and ground nets on a compiled RAM that passes LVS
2654820 nga_use_uti_scale_static_mvmf does not scale static current correctly
2648872 Voltus-XP with report_power_in_parallel true caused an error related to OA
2646560 Incorrect error message when EM models are used for IR analysis
2645369 VSS plot issue in the dynamic IR run
2644492 analyze_resistance is unresponsive
2643097 Add more information to the .report file for the Failed status
2643005 The vector-based run uses more than 2TB when processing events in the unified power flow
2641656 Voltus errors out during the package run
2641423 Huge Cap and ESR difference for standard cells in both the Spectre and non-Spectre flows
2638727 validate_pg_library cannot use the TC current waveform from Voltus-Fi single mode DDV PGV
2638148 XP power analysis fails due to duplicate technology PGV specification
2638094 VTM file generation takes 800GB of RAM
2635707 PGV generation is failing in version 21.13 whereas it is generated successfully in version 20.16
2632320 Correct cap lookup when consuming multi-voltage PGV (.cl) in the single-voltage PGV flow
2632259 Rail analysis error
2632224 Package divergence issue
2631962 Need support for leakage power table generation in case of the mixed trilib flow
2631075 MSMV PGV generation
2625816 VSS current is 0 in the datasheet-based PGV
2622119 Macro PGV generation is failing
2620100 get_activity is not reporting values in Innovus
2620021 IR drop is not crossing a particular via which is preventing rail analysis to get completed
2618009 Backslash and multi-bit are not matching in the SHM VCD run
2617195 what_if_capacitance report generation error
2615527 Need RON interpolation for both LibGen and Voltus-Fi power gate PGV
2614630 PGV: esd_device_check enhancement
2614513 write_die_model in Common UI to support -model_order switch (value 4)
2613947 Handling block-level activity in the top-level run
2612669 Voltus reports a wrong dynamic IR drop for the BIASNW pin of the memories which does not sink any power
2612269 Single RTL to multi-gate and multi-pin mapping is not supported by Voltus
2612094 Need XPGV config file check
2610728 Voltus does not accept the net option for scale_what_if_current
2609160 GUI exits unexpectedly
2607909 Power analysis exits unexpectedly if running with the rEnableStateDepLeakage option
2606507 Voltus errors out during power analysis
2605823 report_power -leakage reports two different total leakage values
2603176 Signal EM checking with signoff extraction fails analysis on certain nets
2603119 How to specify different voltage_threshold_group and report them through report_power?
2600693 VSS.avg.iv file is not sorted by the worst IR Drop
2599391 The power-up run exits unexpectedly
2598891 Enhancement to make NTX as default true in PGV generation
2598623 Vias are not inserted properly
2598092 Support two pin names with CONDITIONAL_PIN for the DDV generation trigger file
2598038 Voltus SHE implementation
2594868 Need to sort the detailed report dumped by report_esd_voltage
2589723 IP-PGV exits unexpectedly
2587906 Tempus ECO exits unexpectedly during eco_opt_design -power when CNOD is enabled
2586887 Port set_rail_analysis_mode -macro_cell_instance_density_file flow to DP
2586098 Common power engine errors out during report_power in Innovus
2584538 report_power issues ::eps::get_power_cmd_file_name error
2583433 Remove some old warning/info messages related to LibGen
2582573 Issue with LSF tolerance in threaded jobs
2582562 LSF job does not finish automatically in DGUI
2581045 PGV enhancement request to trim down the capture time based on the current waveform
2580639 Voltus errors out during the dynamic power target flow
2580152 Need enhancement to improve run time of power report generation
2580077 Autorun RLRP from GUI
2579942 Self-Heating analysis reports a parsing error related to the instance-temperature map file
2579525 TAP cells are annotated as macro pins during propagate_activity
2578842 Message improvement to remove the unnecessary 'DEFAULT' prefix for net names in single die analysis
2578247 Power density vector profiling: report 10 unique power density tiles and pick them automatically based on user input
2578231 Duplicate vector commands generated in the DP mode
2577548 Add a switch to enable dumping of Spice deck for ESR validation
2576059 Improve LibGen resistance extraction and reporting for MIMCAP
2575732 generate_hier_bbv output file name includes backslash character
2573447 Option set_rail_analysis_mode -em_stack_via_check is not supported in the XP mode
2571636 Voltus memory PGV flow did not check the conditional pins in the FSDB file and just took the values in the trigger file
2571617 Voltus exits unexpectedly during analyze_power
2571214 Power analysis takes sum of all PG cap from .lib instead of average
2570705 Issue with NTX misalignment handling
2570614 SHM activity files are not stored in the Innovus database
2570605 IR-aware refine place error
2570110 Cells in the design have multiple power domains but do not have low power constructs in the dotlib file
2568988 LibGen short issue for non-manhattan shapes
2567091 Voltus LUI with the Timing Window file gives drastically different results from CUI or LUI with SDC, no TWF
2567040 Unmask shapes warning
2566886 '-output' switch to 'report_power' is ignored if '-outfile' is also specified
2565648 Spice deck is generated incorrectly for clock mesh signal EM flow
2564975 Voltus errors out during unified power flow analysis
2564310 Voltus exits unexpectedly during SPEF reading
2564295 Power exits unexpectedly due to TWF annotation
2564253 ESR value did not change for memory PGV generation
2563921 Enable block-to-block ranking reuse as part of the top-to-bottom ranking reuse feature
2563815 Segregation of clock domain power report
2561937 Block-level RTL FSDB annotation
2561300 Simultaneous Rise/Fall for clock instance
2561272 Flat power has a problem generating ptiavg for switch net with a backslash
2561167 NTX exits unexpectedly for RDL processing
2561164 Enable the "-beol_delta_temperature _threshold " option in CUI
2561033 gds2def exits unexpectedly
2558563 em_rules_use_layout_dimension does not work in Voltus XP
2557610 Multiple selection capability in the results browser
2557168 NTX color handling error
2556639 Power target flow: Need to set power target through set_power command
2556616 Ramp-up analysis: XP and DP runs show unreasonable reports/plots
2556371 The activity source information from get_activity changes when loading power.db
2554821 NTX RDL disconnects on 45-degree shapes with multi-partition
2554055 Flop annotation is less while the same entry is there in RTL FSDB
2553874 Fanout count is affected due to rEnableMultiSequentialCells
2552186 Unknown option issue in the report_power standalone XP flow
2551503 PGV generation questions related to enable_multi_voltage_cap_generation
2551368 Need an option to waive off some layers during LEF vs PGV check using the check_pg_library command
2549940 PGV is failing with the option fsdb_start_voltage_threshold variable
2548668 PGV run is failing due to Spectre errors
2548448 Wrong VIA width in PGV if there is no width definition in technology LEF file
2547822 Need to reduce memory consumption for boundary_gate_leakage calculation
2546689 Successfully generated and read TCF is corrupted during XP Self-Heat analysis
2546389 How to supply simulator options during Voltus power-grid view generation?
2545199 Power is taking a long time
2544874 IPF flow does not honor the file to assign current
2544621 NTX error
2543824 Voltus error with set_db power_worst_step_size -help
2543479 DEF file is generating invalid manufacturing grid coordinates
2543293 Empty PGV reports were generated for cells with missing LEF in the Voltus-Fi based PGV process
2543217 set_power_rail_layers_nets -via_size is not working
2543014 Voltus exits with generate_power_density
2541710 Need a special license for set_design_mode -process 3 -node N3
2541591 report_power showing different numbers when done twice
2540974 Ability to support triggering different modes for different rails to support FIFO with async frequency
2540761 Rush current analysis does not give meaningful wake up time
2540505 Report all top10 or more worst power duration for each vector
2540244 ChipPwr rPowerReportWorstWindow 1 reports different power values from vector profiling peak power
2539965 Error during XP power analysis around dynamic switch patterns
2539784 ERA-SUBTRACT option does not work in current regions
2538912 MVMF frequency is not matching
2538351 Unable to generate ptiavg file even if the nets have connectivity for primitive instances
2538337 Enhancement required to support mask layers mentioned in the GDS layer map for GDS-based PGV generation
2538333 Need metal-stack-independent GDS-based macro PGV models
2537914 Unified power does not honor worst_window_size with set_power -dynamic_switch_pattern -no_propagation
2537536 The extractor generates the shorting resistors in one vertical line of PG meshes
2537031 Cell state is giving PASS even though there is zero cap value during macro PGV generation
2536341 RTL TCF annotation coverage does not increase by map_activity_file
2535333 PGV macro - VIA2 versus VIA3 discrepancies
2534882 mission_profile -em_temperature option does not work
2534656 Need option to set the switching bit only when the output pin is switching or the DDV current is placed
2532960 exclude_tap_region to support the operation mode defined in the trigger file
2531123 Short check is taking 700GB memory
2530680 Mission profile argument is not available in the common UI for Power EM
2530575 Innovus exits unexpectedly with extra } in the TCF file
2529300 Flops are reported as not scheduled
2528175 Need enhanced techview generation having current distribution based on via density
2526665 PGV generation from the OA layout has incorrect pin shapes
2526300 PGV differences between the 20.10 and 21.11 versions
2525951 Enhancement required to support the trim and mask layers mentioned in the GDS layer map for GDS-based PGV
2524507 Voltus exits unexpectedly while saving the database using the write_db command
2522059 Multi-bit latch should match D -> Q arc independent of scheduling
2521281 Signal EM errors out when using the -toggle option
2521101 Seeing unknown type in the pgv_table report
2520879 report_esd_voltage is not generating the output file
2520241 Need an option to skip signal pin check in the check_pg_library command
2519824 report_irdrop_regions (debug_irdrop) errored out for when using -eiv_method { avg } and { worst avg }
2518985 Memories are not switching in the Voltus dynamic ptiavg file though they are switching in FSDB
2518959 RTL vector-based analysis: power result is not loaded along with the rail results in the XP mode
2518819 get_db does not report leakage for decap after read_power_db
2517850 Domain-based GIF generation errors out
2517537 Rail analysis error
2517066 dump_unannotated_nets needs to allow writing to a directory
2516832 Report different VT cell power and usage in report power
2516243 set_power -pwl -sticky {} command is not honored in the vectorless run
2515439 Cannot generate a macro PGV due to power supply shorts
2514947 Need to print dominant frequency in voltus_power.stateprop.stats
2514730 GDS-based macro PGV merging issue
2514254 Interposer circular bump LEF pin fracturing creates high resistance sliver in few bump instances
2513915 Additional leakage current when using -leakage_scale_factor_for_temp with CCSP
2512650 Need enhancement to capture physical cells in the IPF/design coverage report separately
2510499 NTX should dump to TMPDIR instead of NFS
2509445 Need Voltus to print summary of all check points carried out in the check_pg_library command
2508494 Power exits unexpectedly
2508000 create_die_model capacitance is not matching with the result
2507893 Error message related to current taps is displayed during dynamic rail analysis
2507489 Difference in the behavior of current distribution for ground pins between the XP and non-XP flows
2506875 GDS/Spice integrated macro PGV report is showing the PASS status for zero taps on power nets
2506722 Difference in missing PGV cell list between missingLibModelCell.out and PG integrity report
2506631 Voltus errors out while running the read_activity_file command
2506459 Support for storing multiple cap values in macro PGVs
2504644 Negative toggle time is not able to match CP -> Q Arc
2504535 The RSS flop is not toggling and cannot be force toggled
2504257 Voltus/Innovus/Stylus - Document the -ircx_models option
2503823 Vectorless power change between XP and non-XP
2503708 Zero static currents while generating PGV
2503414 Running report_rail twice causes license check problem
2501987 Dynamic power is reported as 0 in the database-based activity run
2501636 Using enable_spectre_netlist_flow true reports zero ESR, changed coupled cap and Roff for decap and power gates
2500617 Issue with LEF consistency handling for pins with no USE statement defined in LEF
2499863 Incorrect XM block trigger time in the log file
2497881 ‘setvar report_compress_level 2’ or ‘setvar drg_fast_txt_merge true’ are unable to compress the RLRL/EFFR reports
2496337 Voltus errors out during rail analysis
2495834 Wrong toggle rate when reading VCD
2495466 worst.iv and avg.iv are created when -eiv_method is set to worstavg
2494849 New vectorless flow creates leakage-only waveform for dynamic_VSS.ptiavg
2493542 PGV to auto-repeat/splice based on the waveform length for asynchronous DDV
2492890 Voltus errors out when the PTE flow is enabled
2492303 Issue with memory PGV run time and DC convergence on cap characterization
2491386 NTX to extract polygon-shaped vias
2491279 Tap initialization issue when connection between power pin and rail is missing
2489853 Signal EM reports N/A for average limits when lifetime is not specified
2485767 Voltus chip-center thermal flow failed
2485671 Use cap from subckt and extract plate resistance in GDS-based PGV characterization
2485443 Enhance TCL to run PowerDC from Voltus
2484813 MBFF is seeing higher peak current in the first cycle
2484314 Enhancement to overwrite VCD logic state for static power calculation
2484284 get_power transition_density returns negative power
2484009 Voltus does not issue any error/info message when the EM rules are not present in the qrcTechFIle and ICT EM model file
2482337 Signal EM results: Include Ilimit and polynomial equation in the EM attribute form
2482070 Voltus errors out while running the calculate_differential_voltage command
2481963 Provide an option to skip negative time toggle
2481421 Power calculation/vector profiling to support user-driven constraint for cell/instance pin
2479102 rIgnorePhysicalCellsForDSP is causing voltus_power to become unresponsive
2478365 Tool exits unexpectedly during power analysis
2477832 Need an option to control the activity of data network and clock network belonging to a specific hierarchy
2477279 setSignoffOptMode -setup_target_slack_per_view fails when set_power_analysis_mode -enable_view_pruning is true
2477042 LibGen API to allow Spectre to directly read the IP-PGV PWL data from the generated *.cl file
2477034 LibGen to filter the Voltus current PWL data during IP-PGV generation
2476587 Voltus to support rise/fall based EIV file
2475928 iSpatial shows low annotation on IO signals when reading genus2invs.tcf
2475901 Compress the annotation reports
2475309 Need clock scheduler to completely rely on TWF attributes avoiding propagation completely
2474539 Voltus errors out while running the create_die_model command
2473694 Need a debug feature in NTX to print resistor information
2473592 Incomplete net check in the current region flow
2471199 default_dynamic_pgv_mode is not getting triggered in the jitter flow
2471114 UPS flow exits unexpectedly
2469919 Same polarity toggle
2469834 Skip reporting user-specified instances from the IV report
2468047 Only RMS EM result is generated from report_rail
2467997 Memory has not toggled after 7ns and the simulation time is 11ns
2465966 Provide read_activity_file -cell support
2465057 Support multiple ascii_power_file for hierarchical instances
2464365 Need input FSDB waveform dump in addition to the area/peak values during standard cell PGV generation
2463675 Via insertion causing a short
2462822 Use LibGen to find the waveform shaping K factor for every cell
2460582 Incremental CCSP library is not dumped in the Powermeter command file
2459787 Check for incomplete nets
2459190 DGUI query does report the capacitance value
2457864 Automatic creation of region-based die model
2457854 report_power -power_db error
2457698 Ramp-up analysis exits unexpectedly during the simulation stage
2456262 Difference in CNOD leakage calculation between CPE and PM
2456190 EM runtime is longer than the simulation time
2455381 Innovus does not save the correct settings for set_power_analysis_mode
2454344 generate_hier_bbv needs to support xPGV
2453811 debug_irdrop cannot locate the failed tile
2451448 SEM continues even if no EM models are found
2450626 SwitchPatternFail is reported even if dynamic_switch_pattern is set for the DDV instances/cells
2450387 Need an option to exclude "Non top scope nets" from the skipped nets file in the top-scope flow
2450200 Boundary gate leakage power is not reported
2449465 set_db power_view reports obsolete warning of the legacy flow
2447112 Add the beta license features to the -web option
2446745 Discrepancy observed in the RLRP reports
2445494 Voltus does not run power analysis after running XP resistance analysis
2445476 Region-based die model generation needs to support polygon shape of region
2445461 Need an enhancement to issue error messages when the number of nodes is over the limit
2445158 DP rail analysis giving negative EIVs
2445035 Find worst arc and use it for all PG pins
2444708 Always start the current waveform from the nearest resolution
2443394 Support to ignore instances in rail extraction
2443278 Voltus is not honoring the dynamic switch pattern provided by the user
2443150 pg_integrity does not report dropped voltage sources
2442844 generate_esd_rlrp_report: could not write the JSON file while RLRP paths are found
2442578 Vector profile GUI: zoom to activity window automatically
2442293 Getting an error when using set_rail_analysis_config -generate_multi_voltage_library true
2442143 Support conditions with "!" in the trigger file during DDV modeling
2441942 Need different messages for net does not exist and net is flatten
2440641 Inconsistency between the stats and noswitchclockinst files
2439168 Support for user-specified current distribution in multi-height MBFF
2438500 Voltus is not able to generate the standard cell PGV models using the Spectre SPICE files
2437798 set_twf_attribute -clear_twf_attr is unable to reset a lower hierarchy clock frequency
2437690 Need clear and reliable message for distributed runs
2436630 Remove a warning message related to package
2436576 analyze_self_heat is picking glitch power for dtFeol calculation
2435241 switchsrc line count reduces 25X when rNewTwfHandling is enabled
2434058 analyze_rail exits unexpectedly during the reporting stage due to negative voltage rail
2433607 Data from sub-block driving the top-level clock net resulted in switch pattern fail
2433101 Need enhancement to support the CNOD leakage effect in dynamic analysis
2430882 Support bbv_generation for the IP-PGV cell
2430400 Change Reff reporting to include all user-requested nodes
2429486 Self-Heat GUI improvements to include reference temperature and EM
2429481 Thermal analysis flow takes more than 48 hours to complete a single iteration
2429075 Failed to read RTL VCD
2428316 Web browser should start automatically
2426666 Need RLRP tracing based on the worst/best EIV tap/port for all instances
2424406 [Vector Profile] Enhancement to get worst window on each vector
2421784 Enhancement to overwrite the VCD logic state in the dynamic vector-based flow
2421163 validate_pg_library is not working correctly
2420985 Incorrect current waveform captured while using FSDB for PGV generation
2417248 Toggle rate differences between CPE and PM if set_default_switching_activity uses the _ratio options
2416806 Can Voltus provide di/dt in steady-state mode?
2415679 Voltus ERA flow inside Innovus errors out during generate_pg_library
2415465 User-specified current value is not used for domain-based rail analysis in the XP flow
2414534 Need debug report that lists invalid arcs
2414529 Incorrect TWF delay interpretation
2408111 Include Ilimit and polynomial equation in the EM attribute form
2400380 Generate multiple macro block LEFs and keep the block pin name by GDS2DEF
2399697 EM results filtering capability for the block ports
2399115 Simulation stops because of case sensitivity
2365472 Voltus extractor exits unexpectedly during rail analysis
2364613 Typo in power reporting
2364465 False EM violation in the AP layer
2360854 Narrow width resistance potentially causes false EM error
2360709 Provide an option to modify the PWL units in the current region file
2357897 'report_power' leaves huge text files after running
2357276 Voltus is not honoring the leakage power when provided through set_power
2355434 Dynamic voltage waveform loading takes nearly 20mins
2355346 Current peak distance is increasing period after period
2353562 set_db check_ac_limit_detailed true does not work
2352761 Macro output is being scheduled for pin with no timing
2349753 Distributed Power - rNetSwitchingActivity and rPinSwitchingActivity commands are missing
2349697 Error for set_power_data -format area if the net name contains slash
2346868 Update TCL to run SpeedEM and PowerDC from Voltus
2344868 Need enhancement for map_activity_file to inverse the duty for QN
2328239 Print TWF stats information in the Voltus log and power.missing_data.twf file
2323853 set_power cannot support block name power assignment
2309242 Cell viewer showed fly line in the EM view of 20.1 PGV, but detailed information in 19.1 PGV
2293267Give an option to combine reports without lighter version of power analysis
2288122 analyze_resistance: dump layer name and pin XY location in the output report
2280355 "Node Reff" value is "0" instead of "NA"
2277043 Enhancement to set the VU threshold value
2272900 Voltus XP reports 0.226kA with a set power of 4.5W
2271692 Need a new -current_generation_method that does both peak preservation as well as charge preservation in the dynamic current waveform
2267338 LibGen macro PGV generation exits unexpectedly
2259254 Voltus needs to include the unconnected instances to be present in the default rail ptiavg
2256440 Need additional enhancements to the itaputil utility
2250345 DGUI: Need some information about machine waiting/status/acquisition in the terminal and log
2246964 Die model flow uses very high disk memory
2241513 dynamic_switch_pattern { - - } is not honored with -no_propagation
2238671 Add the Stylus command for report_instances_missing_current_data
2209216 Support different dynamic power mode per DP block
2180593 set_power -ascii_power_file needs support for loading gzipped files
2173934 Enable RLRP analysis (layer-based resistance reporting) in the ESD B2C flow
2109507 Option to change the VSRC and node (VIA) size on the fly
1997150 Default unit change of em_conductor_unit and em_via_area_unit
1993851 Accurate supply current modeling for resistive shielding
1973563 Need to remove the warning message ‘No valid current data found to perform dynamic analysis’ when there are valid current regions
1964608 Rail needs to handle NA in pg_trigger during the VCD-based power-up analysis
1961552 Need an option to calculate path length with summing of all connected metal segments
1833148 ICT EM syntax support - ANTI_DERATE
August 09, 2022
Fixed CCRs in Tempus 22.10 RTM
=================================================
2670028 Some designs error out in some cases
2663928 Cpl on a bidi net goes away when bus_attacker_accuracy_mode 4 or estimate_glitch_method 3 are used
2663817 Library loading errors out while reading and merging aging libraries
2661926 get_property does not return timing point name in DSTA
2657163 save_design does not create link of libs compressed in .gz format, while saving db in DSTA CUI and LUI flows
2651587 DSTA not recognizing variable inside get_db
2644953 High transition values reported in ETM library generation
2644534 IPD) High scope size in bounded corner run (SMMC with max min corner) is not bounded in max corner (SMSC run)
2643424 Tempus has inconsistent handling/merging of single-edge clocks at multi-input gate
2642725 Context beta feature is required in DSTA - but not STA
2641606 Incorrect reports with null clock/garbage nets for report_noise -style detailed in DSTA-CUI
2641484 Large negative delay on through pad
2632814 Separate EM/corner library add to base timing/corner library
2632738 SEGV in report_noise -sort_by slack -gui_victim_nets_file
2631026 Generate SDF similar to SDF generated without retain data in some cases
2630663 Make set_si_mode -eco_accuracy_mode 1 default
2627060 DSTA CUI - proper message to be provided in case of no machine available
2626374 Stack trace during CCS-TN noise Liberty model only
2625755 report_timing -retime_max_slack does not report paths unless -max_slack is >= PBA slack
2624938 ERROR: (TA-1029) *DIAG:(Missing Adj)
2624435 Improve Tempus heuristic for inferring voltage/temp when exact match is not found
2624431 Tempus binds set_driving_cell library to wrong voltage in some designs
2623926 update_timing -full errors out
2613954 Report fields are getting merged together instead of having spaces between them
2612035 Stack trace with set_annotated_delay -cell
2611688 Voltage interpolation when one of the voltages is constant
2609725 Errors during check_timing -verbose -tcl_list
2609372 Tempus errors out during set_delay_cal_mode -use_diff_volt_in_eiv_timing_analysis run
2606690 Add newNetname option to the addRepeater command
2605711 report_noise writes out .rn files in the local directory
2604167 Huge memory used when reading libraries
2603096 API tomIsCteDelaysUpdated returning false for a STA client saved with update_glitch
2601503 Package Paradime improvement settings or make default
2598796 When Paradime client errors out, the status of the other clients be placed into the log file
2598761 **ERROR: (SCOPE-2493): Error in writing consistency data
2598251 Syntax error TA-120 while reading SDF
2597097 Tempus errors out after merge_timing_reports command run
2592491 set_clock_exclusivity for generated clocks of same master clock at output of Mux
2592420 Voltus errors out at handling SDC with segmentation fault core dump
2592091 Enhance write_ldb to eliminate check on TECHLIB-1277 WARN to generate LDB file
2591797 ROP calculation is affected by change of reporting thresholds from set_glitch_threshold
2590441 Errors due to index not found
2588222 Tempus errors out on report_timing -retime
2587394 Request for new property for borrow-edge-adjust - is_borrow_edge_adjust
2582167 get_db attributes do not provide information in DSTA
2580297 Uniquify the empty module names so that they do not collide across boundary models
2579608 update_glitch errors out with LC
2579558 report_noise errors out with LC and many attackers as well as boundary model
2577611 Valus is issuing TECHLIB-1445 even when state_function or statetable is present
2574836 SLBBV to come to the same order of analysis views when same libraries are read
2574000 Tempus errors out while restoring the design
2572257 Issue a warning message when boundary model is read from a different version
2565483 CPPR calculation difference between versions
2565443 CCR to track the documentation of all DSTA error messages reporting in master log
2565433 Boundary model to give proper warning, if there is a problem during creation
2564854 "set_db timing_report_enable_cppr_point true" or "-debug cppr_point" does not work for Stylus format report_timing
2563803 Tempus errors out for several hours after "reset_clock"
2561103 Tempus consumes excessive memory and does not release it during do_extract_model
2560448 CTE runtime hit during update_glitch
2560173 DSTA-CUI: Tempus errors out while saving the design post distribute_partition
2558822 High runtime during outside partition marking
2558794 read_spef to give error, if boundary model SPEF is deleted between set_top_module and read_spef
2558194 Long runtime due to clock nets with fanout > 1000
2554489 Change default limit of 100s for Valus to catch big numbers in .lib
2553709 Request a warning message any time the RIP > VDD
2553705 Support an option for Tempus to exit if the boundary model is deleted while Tempus is running
2552565 report_noise to write temp files to TMPDIR instead of local directory
2551843 Ignore endpoints to modules with missing libraries when creating a boundary model and issue a warning
2551615 Different vdd's leading to large area/width
2550226 N3 base delay has outlier during voltage extrapolation
2548951 Add an option in read_boundary_model to skip endpoint tracing for empty modules
2548864 Provide a way to skip net(s) from being loaded from the boundary model
2548810 List each boundary model as it is being read in
2548214 Errors when using testcase with boundary model
2547805 Stack trace while generating annotation summary
2547527 Several hours runtime for report_annotated_delay, after read_sdf with 16 threads
2547471 Tempus PBA result is worse than GBA result
2547099 Document list_libraries "-used" and "-used_analysis" options
2545266 DSTA CUI: Tempus saves original Verilog netlist path instead of IMEX::dataVar while saving design
2542765 DSTA CUI: Tempus does not dump relative library path or path absolute to design DB saved by write_db
2541680 Provide a metric in log file, such as runtime histogram, for understanding runtime
2541679 Make set_delay_cal_mode -eng_bugFixLC true default
2541026 Errors in update_glitch
2539792 Add Tempus ECO xtalk and glitch support over cell-edge + net-edge, i.e., delta_delay_annotation_mode arc
2539780 Remove spaces between libraries in custom glitch report
2539778 Issue a warning message when area or width are large
2539176 DSTA CUI: Getting DPO as result on querying name of rc_corner
2538203 Ensure there is a space between values in glitch report
2536090 SDF errors TA-120 during report_annotated_delay after read_sdf
2535732 Merged ETM libs with different merging modes and having identical timing tables are printed separately
2535387 DSTA CUI errors out during report_clock_timing
2534780 Errors in update_glitch on full chip design
2532419 Unreasonable incremental delay for a net
2531750 Support an option to output TECHLIB messages for cells used in the design only
2528568 Some Tempus versions show CPPR point difference
2524933 Errors in some Tempus builds
2522303 Restore design, followed by update_library_set, context is not getting re-loaded
2520900 report_delay_calculation -si is not giving aggressor net information
2520752 Bus ATT less than IAT should be able to be set as quiet_attacker
2515667 Tempus ECO timing does not converge after ECOs implemented in Innovus
2515552 Fix for checking if define_bundled_bus nets are PG nets, does not work when Verilog uses n({VSS, VSS}) type syntax
2513616 Innovus errors out during SignoffOptDesign
2512355 DSTA CUI is returning some collection (get_db), even when pattern is not found
2512174 CUI command create_cell_signal_em_model errors out when using read_libs -max_libs
2511927 Errors in report_noise
2510741 Errors in infer_pgv_intent in some cases
2509066 Errors in create_glitch_boundary_model when testcase is missing DCAP lib
2507770 All sequentials are not all_registers
2507699 ETM generated is not capturing in2out path
2507398 DSTA exits with error "IMPTCM-48" while reading power content information from CPF
2506842 report_timing_derate does not report power domain based net derate, reports power domain based cell derate
2506429 Number of fields and headers should match in glitch report
2506423 IMPESI-3428 to check if net is PG net
2505449 Tempus errors out upon execution of "distribute_report_runtime" command
2501916 Area and width is merged together
2499964 Tempus/Innovus DB restore errors out when set_quiet_attacker references inactive analysis view
2499494 Add the total number of nets to the progress report
2498738 Errors in Paradime run in AAE
2498736 Errors in Paradime during report_bus_bundle with bus merging
2498734 Errors during Paradime run
2498197 Several timing path properties are not mapped in get_db, when compared with report_property
2497779 update_delay_corner -irdrop_data(file) does not annotate
2497389 Boundary model flow not working in CUI - exiting with error "I(MPIMEX-12): 'init_design' failed"
2496648 get_db mapping required for properties of report_noise -collection
2496236 Errors in report_noise
2496020 User-defined attributes issue in Tempus DSTA Stylus mode
2494459 report_noise -collection to include slack values
2493482 Add new message if net is PG net for IMPESI-3019 and IMPESI-3018 checks
2493423 Change nobus behavior with LC
2492802 DC Tol happening instead of ROP due to numerical instability
2491299 While fixing Hold in hold path group, Setup degrades in Tempus HC-ECO
2490585 Incorrect numbers showing up in glitch report
2488093 get_db analysis_view .is_active and all_analysis_view -type active shows different result in DSTA CUI mode
2488083 Tab option with get_db does not work in DSTA CUI mode
2487750 Voltage interpolation for Macros support
2487730 Need "create_property_alias" support in DSTA
2487545 Tempus Paradime errors out during eco_opt_design
2483288 report_noise -collection does not work if delay switch is specified
2483285 report_noise -collection does not work in DSTA CUI mode
2481249 set_delay_cal_mode -doonly {netnames} to issue a WARN if the net names are not valid
2481229 [get_db current_design] is not supported before distribute_partition
2480940 Add (Threshold) header back into ROP portion of glitch report when format option is specified
2480939 Verbose LC reporting is causing errors in glitch reporting
2480853 Support B: & ~B: in report for the net name
2480534 DSTA CUI: Command related information not dumped in client log file and commands not dumped in command log
2476232 Errors during report_timing -collection run
2474405 Bus bits that are connected to one instance only are not printed in bundle file
2471491 DMMMC master not exiting even though client jobs errored out
2470769 Errors at msvCheckSourceSinkDiffSupply() during commit_power_intent after read_design
2469618 eval_legacy {get_delay_cal_mode} is not working in distributed mode Stylus run
2469606 eval_legacy {get_si_mode} is not working in distributed mode Stylus run
2465137 Support for write_db -user_path
2464523 Incorrect reporting for early/late_clock/data_pg_net_voltages with IRDB annotation
2463559 report_timing_derate does not report timing derate of all power domains link/bind to specific delay corner
2462179 Wrong setup check time in Tempus client in signoffTimeDesign with IRDB
2461876 save_design errors out while running DSTA in Stylus mode
2461376 WARN: (IMPESI-3468): User needs to specify -equivalent_waveform_model propagation first before specifying -w
2461363 **WARN: (UI-338): Variable 'timing_enable_wire_load_model_support' is obsolete and has been replaced
2461130 Tempus not returning worst path
2461099 distribute_design_views to support the passing of the "invs" license with "-lic_startup_extra invs"
2459639 New attribute on generated clocks with all the pins from the master clock root
2459627 Switching capacitance in the glitch report needs to show the analysis switching capacitance
2459456 Delay Calculation first iteration run in constraint delay-corner update run on a restored session
2457981 Disable clock assertion after timing context is read to avoid errors
2457758 SPICE ground capacitance for the victim is larger than the SPEF ground cap
2457731 Add control for limiting how many busVAs are included in the simulation
2457460 report_timing_derate does not report derates of all power domains bind to delay corner, report_timing reports
2456551 Unexpected glitch violation
2456079 Check if bus bundle net is power/ground and issue a warning
2455899 ETM generation takes several hours in some cases
2455716 Combinational arc for a port not characterized in ETM
2455692 set_instance_library used but terminal voltage taken from PG net voltage assignment
2454240 current_design returns null value in Tempus STA run and reports error in DSTA run
2452946 SPICE deck with expand bus enabled should write out all the attackers
2452798 Incorrect minimum rise delay reported
2452596 Tempus errors out while echoing any variable in distributed mode
2450183 Report only ACT attackers in the glitch report
2449548 set_pll_timing changes the slew at output of PLL
2448484 report_noise -quiet_nets with set_quiet_aggressor -aggressor does not show small aggressors
2448377 Missing OCV on output pins
2448091 Request to verify all necessary files are present for glitch boundary model
2448088 Attacker state for busVA components needs to be reported with glitch properties
2447608 IMPESI-3194 seen in PGV Flow
2446345 Applying the boundary model constraints should not exit, if there is an error with one
2444002 PBA slack not bounded with GBA, when set_input_delay is used with reference_pin
2443172 Use Prp noise for estimated glitch when determining if glitch will be simulated or not in the 2nd iteration
2442861 High runtime with leakage ECO with low fix rate and .summary file not getting dumped
2441443 CPU HC ECO client errors out during delete_repeater
2440618 High retime slew for INV cell
2440312 apply_boundary_model_constraints does not accept a - in the bus bundle name
2439329 Flop with large timing difference between signoffTimeDesign with Tempus and Tempus-PI
2435053 When IMPESI-3345 is issued, the failure criteria should change from ROP to RIP
2434416 set_cdb_binding is not logged in the logv/cmd file
2434398 Larger than expected runtime increase of bus over nobus run
2433785 Tempus DSTA errors out due to large number of comments in SPEF file
2429552 Paths go unconstrained inconsistently in C-MMMC
2429475 Tempus eco_opt_design -power degrades setup time
2427620 report_noise should not print list of nets or pins in the glitch report
2427005 Request to add 'Function' attribute for Feedthrough Port
2420705 Support to override the UDN failure criteria
2417838 Show info message when reading in constraints from boundary model
2415896 lib_arc mode attribute should support multiple etm_modes per arc
2412082 Need CUI mapping for set_eco_opt_mode -add_inv_pair
2400573 Voltus and Innovus not aligned for check_connectivity options
2365392 Need CUI command/variable for set_si_mode -si_reselection_glitch_threshold
2364603 write_timing_model (do_extract_model) SEGV
2362411 ETM not generated with MT enable
2360565 Apply LC to bus bits in bus attacker
2356192 Dynamic net derate of 1.0 is not considered
2352669 Request to dump last net(s) analyzed when run appears to be low on memory
2321074 Generate correct stimuli file automatically when generating Spice netlist
2309966 CUI equivalent option of -include_used_subckt of create_spice_deck command
2308031 Differentiate GBA slacks based on nworst and max_paths for incomplete or leftover endpoints in EPBA timing report
2305098 Request to merge bus groups together from block boundaries during top level run
2301793 Invalid value 'enum' specified with '-retime' for 'report_chain'
2291399 Tempus voltage difference physical vs logical mode, read_design -mmmcFile -setup_views -hold_views -dynamic_view -leakage_view
2278476 Limit the number of attackers before bundling for the bus
2272364 Add local clock skew details to report_timing timing report
2262403 Need check_timing option to sort verbose report by check type and not pin
2260680 merge_timing_reports in CUI is dropping path header information
2232843 Need to support "get_pins ./<somepin>" relative to a current_instance
2198804 opt_signoff is not working in some cases
2191274 Correct the spelling of characterization in timing_extract_model_enable_context_independent_latch_thru_charaterization
2184670 Put WARN messages around UDN warnings and indicate which cell they belong to
2183961 Add the glitch type to the IMPESI-3205 message about small injected noise
2115237 set_clock_sense -negative not generating correct clock
2101199 Valus does not raise any warning/error message for negative and junk sigma timing check values
2089054 CPE and PM modes report incorrect state dependent leakage
2078022 Enhance Innovus to fix overshoot/undershoot violations
2028397 Report glitch analysis progress in the log file - to indicate run is progressing
2022874 Multiple options of check_legacy_design not working in Tempus Stylus
1786676 Incorrect error in Valus Liberty validation for missing 'timing_sense' attribute, even if 'timing_type' is already present
=================================================
Fixed CCRs in Voltus 22.10 RTM
=================================================
2677674 Voltus errors out during rail analysis
2674363 Voltus errors out during the simulation stage
2671531 VTM flow does not consider sub-block orientation for power map generation
2669921 Voltus errors out when running report_rail in the XP mode with report_power in parallel and 3rd party Extended SPEF
2667152 generate_pg_library fails to calculate the current distribution
2664326 CUI should support set_power_analysis_mode -auto_distribute -auto_distribute_threshold
2662172 validate_pg_library does not honor cell foreign
2657443 averagedump of TC_SUM is greater than the averagedump of the dynamic ptiavg file
2656542 CCS current increases with run time when using the CCS library for vectorless and state propagation
2656290 Voltus PGV generation fails flagging shorts between power and ground nets on a compiled RAM that passes LVS
2654820 nga_use_uti_scale_static_mvmf does not scale static current correctly
2648872 Voltus-XP with report_power_in_parallel true caused an error related to OA
2646560 Incorrect error message when EM models are used for IR analysis
2645369 VSS plot issue in the dynamic IR run
2644492 analyze_resistance is unresponsive
2643097 Add more information to the .report file for the Failed status
2643005 The vector-based run uses more than 2TB when processing events in the unified power flow
2641656 Voltus errors out during the package run
2641423 Huge Cap and ESR difference for standard cells in both the Spectre and non-Spectre flows
2638727 validate_pg_library cannot use the TC current waveform from Voltus-Fi single mode DDV PGV
2638148 XP power analysis fails due to duplicate technology PGV specification
2638094 VTM file generation takes 800GB of RAM
2635707 PGV generation is failing in version 21.13 whereas it is generated successfully in version 20.16
2632320 Correct cap lookup when consuming multi-voltage PGV (.cl) in the single-voltage PGV flow
2632259 Rail analysis error
2632224 Package divergence issue
2631962 Need support for leakage power table generation in case of the mixed trilib flow
2631075 MSMV PGV generation
2625816 VSS current is 0 in the datasheet-based PGV
2622119 Macro PGV generation is failing
2620100 get_activity is not reporting values in Innovus
2620021 IR drop is not crossing a particular via which is preventing rail analysis to get completed
2618009 Backslash and multi-bit are not matching in the SHM VCD run
2617195 what_if_capacitance report generation error
2615527 Need RON interpolation for both LibGen and Voltus-Fi power gate PGV
2614630 PGV: esd_device_check enhancement
2614513 write_die_model in Common UI to support -model_order switch (value 4)
2613947 Handling block-level activity in the top-level run
2612669 Voltus reports a wrong dynamic IR drop for the BIASNW pin of the memories which does not sink any power
2612269 Single RTL to multi-gate and multi-pin mapping is not supported by Voltus
2612094 Need XPGV config file check
2610728 Voltus does not accept the net option for scale_what_if_current
2609160 GUI exits unexpectedly
2607909 Power analysis exits unexpectedly if running with the rEnableStateDepLeakage option
2606507 Voltus errors out during power analysis
2605823 report_power -leakage reports two different total leakage values
2603176 Signal EM checking with signoff extraction fails analysis on certain nets
2603119 How to specify different voltage_threshold_group and report them through report_power?
2600693 VSS.avg.iv file is not sorted by the worst IR Drop
2599391 The power-up run exits unexpectedly
2598891 Enhancement to make NTX as default true in PGV generation
2598623 Vias are not inserted properly
2598092 Support two pin names with CONDITIONAL_PIN for the DDV generation trigger file
2598038 Voltus SHE implementation
2594868 Need to sort the detailed report dumped by report_esd_voltage
2589723 IP-PGV exits unexpectedly
2587906 Tempus ECO exits unexpectedly during eco_opt_design -power when CNOD is enabled
2586887 Port set_rail_analysis_mode -macro_cell_instance_density_file flow to DP
2586098 Common power engine errors out during report_power in Innovus
2584538 report_power issues ::eps::get_power_cmd_file_name error
2583433 Remove some old warning/info messages related to LibGen
2582573 Issue with LSF tolerance in threaded jobs
2582562 LSF job does not finish automatically in DGUI
2581045 PGV enhancement request to trim down the capture time based on the current waveform
2580639 Voltus errors out during the dynamic power target flow
2580152 Need enhancement to improve run time of power report generation
2580077 Autorun RLRP from GUI
2579942 Self-Heating analysis reports a parsing error related to the instance-temperature map file
2579525 TAP cells are annotated as macro pins during propagate_activity
2578842 Message improvement to remove the unnecessary 'DEFAULT' prefix for net names in single die analysis
2578247 Power density vector profiling: report 10 unique power density tiles and pick them automatically based on user input
2578231 Duplicate vector commands generated in the DP mode
2577548 Add a switch to enable dumping of Spice deck for ESR validation
2576059 Improve LibGen resistance extraction and reporting for MIMCAP
2575732 generate_hier_bbv output file name includes backslash character
2573447 Option set_rail_analysis_mode -em_stack_via_check is not supported in the XP mode
2571636 Voltus memory PGV flow did not check the conditional pins in the FSDB file and just took the values in the trigger file
2571617 Voltus exits unexpectedly during analyze_power
2571214 Power analysis takes sum of all PG cap from .lib instead of average
2570705 Issue with NTX misalignment handling
2570614 SHM activity files are not stored in the Innovus database
2570605 IR-aware refine place error
2570110 Cells in the design have multiple power domains but do not have low power constructs in the dotlib file
2568988 LibGen short issue for non-manhattan shapes
2567091 Voltus LUI with the Timing Window file gives drastically different results from CUI or LUI with SDC, no TWF
2567040 Unmask shapes warning
2566886 '-output' switch to 'report_power' is ignored if '-outfile' is also specified
2565648 Spice deck is generated incorrectly for clock mesh signal EM flow
2564975 Voltus errors out during unified power flow analysis
2564310 Voltus exits unexpectedly during SPEF reading
2564295 Power exits unexpectedly due to TWF annotation
2564253 ESR value did not change for memory PGV generation
2563921 Enable block-to-block ranking reuse as part of the top-to-bottom ranking reuse feature
2563815 Segregation of clock domain power report
2561937 Block-level RTL FSDB annotation
2561300 Simultaneous Rise/Fall for clock instance
2561272 Flat power has a problem generating ptiavg for switch net with a backslash
2561167 NTX exits unexpectedly for RDL processing
2561164 Enable the "-beol_delta_temperature _threshold " option in CUI
2561033 gds2def exits unexpectedly
2558563 em_rules_use_layout_dimension does not work in Voltus XP
2557610 Multiple selection capability in the results browser
2557168 NTX color handling error
2556639 Power target flow: Need to set power target through set_power command
2556616 Ramp-up analysis: XP and DP runs show unreasonable reports/plots
2556371 The activity source information from get_activity changes when loading power.db
2554821 NTX RDL disconnects on 45-degree shapes with multi-partition
2554055 Flop annotation is less while the same entry is there in RTL FSDB
2553874 Fanout count is affected due to rEnableMultiSequentialCells
2552186 Unknown option issue in the report_power standalone XP flow
2551503 PGV generation questions related to enable_multi_voltage_cap_generation
2551368 Need an option to waive off some layers during LEF vs PGV check using the check_pg_library command
2549940 PGV is failing with the option fsdb_start_voltage_threshold variable
2548668 PGV run is failing due to Spectre errors
2548448 Wrong VIA width in PGV if there is no width definition in technology LEF file
2547822 Need to reduce memory consumption for boundary_gate_leakage calculation
2546689 Successfully generated and read TCF is corrupted during XP Self-Heat analysis
2546389 How to supply simulator options during Voltus power-grid view generation?
2545199 Power is taking a long time
2544874 IPF flow does not honor the file to assign current
2544621 NTX error
2543824 Voltus error with set_db power_worst_step_size -help
2543479 DEF file is generating invalid manufacturing grid coordinates
2543293 Empty PGV reports were generated for cells with missing LEF in the Voltus-Fi based PGV process
2543217 set_power_rail_layers_nets -via_size is not working
2543014 Voltus exits with generate_power_density
2541710 Need a special license for set_design_mode -process 3 -node N3
2541591 report_power showing different numbers when done twice
2540974 Ability to support triggering different modes for different rails to support FIFO with async frequency
2540761 Rush current analysis does not give meaningful wake up time
2540505 Report all top10 or more worst power duration for each vector
2540244 ChipPwr rPowerReportWorstWindow 1 reports different power values from vector profiling peak power
2539965 Error during XP power analysis around dynamic switch patterns
2539784 ERA-SUBTRACT option does not work in current regions
2538912 MVMF frequency is not matching
2538351 Unable to generate ptiavg file even if the nets have connectivity for primitive instances
2538337 Enhancement required to support mask layers mentioned in the GDS layer map for GDS-based PGV generation
2538333 Need metal-stack-independent GDS-based macro PGV models
2537914 Unified power does not honor worst_window_size with set_power -dynamic_switch_pattern -no_propagation
2537536 The extractor generates the shorting resistors in one vertical line of PG meshes
2537031 Cell state is giving PASS even though there is zero cap value during macro PGV generation
2536341 RTL TCF annotation coverage does not increase by map_activity_file
2535333 PGV macro - VIA2 versus VIA3 discrepancies
2534882 mission_profile -em_temperature option does not work
2534656 Need option to set the switching bit only when the output pin is switching or the DDV current is placed
2532960 exclude_tap_region to support the operation mode defined in the trigger file
2531123 Short check is taking 700GB memory
2530680 Mission profile argument is not available in the common UI for Power EM
2530575 Innovus exits unexpectedly with extra } in the TCF file
2529300 Flops are reported as not scheduled
2528175 Need enhanced techview generation having current distribution based on via density
2526665 PGV generation from the OA layout has incorrect pin shapes
2526300 PGV differences between the 20.10 and 21.11 versions
2525951 Enhancement required to support the trim and mask layers mentioned in the GDS layer map for GDS-based PGV
2524507 Voltus exits unexpectedly while saving the database using the write_db command
2522059 Multi-bit latch should match D -> Q arc independent of scheduling
2521281 Signal EM errors out when using the -toggle option
2521101 Seeing unknown type in the pgv_table report
2520879 report_esd_voltage is not generating the output file
2520241 Need an option to skip signal pin check in the check_pg_library command
2519824 report_irdrop_regions (debug_irdrop) errored out for when using -eiv_method { avg } and { worst avg }
2518985 Memories are not switching in the Voltus dynamic ptiavg file though they are switching in FSDB
2518959 RTL vector-based analysis: power result is not loaded along with the rail results in the XP mode
2518819 get_db does not report leakage for decap after read_power_db
2517850 Domain-based GIF generation errors out
2517537 Rail analysis error
2517066 dump_unannotated_nets needs to allow writing to a directory
2516832 Report different VT cell power and usage in report power
2516243 set_power -pwl -sticky {} command is not honored in the vectorless run
2515439 Cannot generate a macro PGV due to power supply shorts
2514947 Need to print dominant frequency in voltus_power.stateprop.stats
2514730 GDS-based macro PGV merging issue
2514254 Interposer circular bump LEF pin fracturing creates high resistance sliver in few bump instances
2513915 Additional leakage current when using -leakage_scale_factor_for_temp with CCSP
2512650 Need enhancement to capture physical cells in the IPF/design coverage report separately
2510499 NTX should dump to TMPDIR instead of NFS
2509445 Need Voltus to print summary of all check points carried out in the check_pg_library command
2508494 Power exits unexpectedly
2508000 create_die_model capacitance is not matching with the result
2507893 Error message related to current taps is displayed during dynamic rail analysis
2507489 Difference in the behavior of current distribution for ground pins between the XP and non-XP flows
2506875 GDS/Spice integrated macro PGV report is showing the PASS status for zero taps on power nets
2506722 Difference in missing PGV cell list between missingLibModelCell.out and PG integrity report
2506631 Voltus errors out while running the read_activity_file command
2506459 Support for storing multiple cap values in macro PGVs
2504644 Negative toggle time is not able to match CP -> Q Arc
2504535 The RSS flop is not toggling and cannot be force toggled
2504257 Voltus/Innovus/Stylus - Document the -ircx_models option
2503823 Vectorless power change between XP and non-XP
2503708 Zero static currents while generating PGV
2503414 Running report_rail twice causes license check problem
2501987 Dynamic power is reported as 0 in the database-based activity run
2501636 Using enable_spectre_netlist_flow true reports zero ESR, changed coupled cap and Roff for decap and power gates
2500617 Issue with LEF consistency handling for pins with no USE statement defined in LEF
2499863 Incorrect XM block trigger time in the log file
2497881 ‘setvar report_compress_level 2’ or ‘setvar drg_fast_txt_merge true’ are unable to compress the RLRL/EFFR reports
2496337 Voltus errors out during rail analysis
2495834 Wrong toggle rate when reading VCD
2495466 worst.iv and avg.iv are created when -eiv_method is set to worstavg
2494849 New vectorless flow creates leakage-only waveform for dynamic_VSS.ptiavg
2493542 PGV to auto-repeat/splice based on the waveform length for asynchronous DDV
2492890 Voltus errors out when the PTE flow is enabled
2492303 Issue with memory PGV run time and DC convergence on cap characterization
2491386 NTX to extract polygon-shaped vias
2491279 Tap initialization issue when connection between power pin and rail is missing
2489853 Signal EM reports N/A for average limits when lifetime is not specified
2485767 Voltus chip-center thermal flow failed
2485671 Use cap from subckt and extract plate resistance in GDS-based PGV characterization
2485443 Enhance TCL to run PowerDC from Voltus
2484813 MBFF is seeing higher peak current in the first cycle
2484314 Enhancement to overwrite VCD logic state for static power calculation
2484284 get_power transition_density returns negative power
2484009 Voltus does not issue any error/info message when the EM rules are not present in the qrcTechFIle and ICT EM model file
2482337 Signal EM results: Include Ilimit and polynomial equation in the EM attribute form
2482070 Voltus errors out while running the calculate_differential_voltage command
2481963 Provide an option to skip negative time toggle
2481421 Power calculation/vector profiling to support user-driven constraint for cell/instance pin
2479102 rIgnorePhysicalCellsForDSP is causing voltus_power to become unresponsive
2478365 Tool exits unexpectedly during power analysis
2477832 Need an option to control the activity of data network and clock network belonging to a specific hierarchy
2477279 setSignoffOptMode -setup_target_slack_per_view fails when set_power_analysis_mode -enable_view_pruning is true
2477042 LibGen API to allow Spectre to directly read the IP-PGV PWL data from the generated *.cl file
2477034 LibGen to filter the Voltus current PWL data during IP-PGV generation
2476587 Voltus to support rise/fall based EIV file
2475928 iSpatial shows low annotation on IO signals when reading genus2invs.tcf
2475901 Compress the annotation reports
2475309 Need clock scheduler to completely rely on TWF attributes avoiding propagation completely
2474539 Voltus errors out while running the create_die_model command
2473694 Need a debug feature in NTX to print resistor information
2473592 Incomplete net check in the current region flow
2471199 default_dynamic_pgv_mode is not getting triggered in the jitter flow
2471114 UPS flow exits unexpectedly
2469919 Same polarity toggle
2469834 Skip reporting user-specified instances from the IV report
2468047 Only RMS EM result is generated from report_rail
2467997 Memory has not toggled after 7ns and the simulation time is 11ns
2465966 Provide read_activity_file -cell support
2465057 Support multiple ascii_power_file for hierarchical instances
2464365 Need input FSDB waveform dump in addition to the area/peak values during standard cell PGV generation
2463675 Via insertion causing a short
2462822 Use LibGen to find the waveform shaping K factor for every cell
2460582 Incremental CCSP library is not dumped in the Powermeter command file
2459787 Check for incomplete nets
2459190 DGUI query does report the capacitance value
2457864 Automatic creation of region-based die model
2457854 report_power -power_db error
2457698 Ramp-up analysis exits unexpectedly during the simulation stage
2456262 Difference in CNOD leakage calculation between CPE and PM
2456190 EM runtime is longer than the simulation time
2455381 Innovus does not save the correct settings for set_power_analysis_mode
2454344 generate_hier_bbv needs to support xPGV
2453811 debug_irdrop cannot locate the failed tile
2451448 SEM continues even if no EM models are found
2450626 SwitchPatternFail is reported even if dynamic_switch_pattern is set for the DDV instances/cells
2450387 Need an option to exclude "Non top scope nets" from the skipped nets file in the top-scope flow
2450200 Boundary gate leakage power is not reported
2449465 set_db power_view reports obsolete warning of the legacy flow
2447112 Add the beta license features to the -web option
2446745 Discrepancy observed in the RLRP reports
2445494 Voltus does not run power analysis after running XP resistance analysis
2445476 Region-based die model generation needs to support polygon shape of region
2445461 Need an enhancement to issue error messages when the number of nodes is over the limit
2445158 DP rail analysis giving negative EIVs
2445035 Find worst arc and use it for all PG pins
2444708 Always start the current waveform from the nearest resolution
2443394 Support to ignore instances in rail extraction
2443278 Voltus is not honoring the dynamic switch pattern provided by the user
2443150 pg_integrity does not report dropped voltage sources
2442844 generate_esd_rlrp_report: could not write the JSON file while RLRP paths are found
2442578 Vector profile GUI: zoom to activity window automatically
2442293 Getting an error when using set_rail_analysis_config -generate_multi_voltage_library true
2442143 Support conditions with "!" in the trigger file during DDV modeling
2441942 Need different messages for net does not exist and net is flatten
2440641 Inconsistency between the stats and noswitchclockinst files
2439168 Support for user-specified current distribution in multi-height MBFF
2438500 Voltus is not able to generate the standard cell PGV models using the Spectre SPICE files
2437798 set_twf_attribute -clear_twf_attr is unable to reset a lower hierarchy clock frequency
2437690 Need clear and reliable message for distributed runs
2436630 Remove a warning message related to package
2436576 analyze_self_heat is picking glitch power for dtFeol calculation
2435241 switchsrc line count reduces 25X when rNewTwfHandling is enabled
2434058 analyze_rail exits unexpectedly during the reporting stage due to negative voltage rail
2433607 Data from sub-block driving the top-level clock net resulted in switch pattern fail
2433101 Need enhancement to support the CNOD leakage effect in dynamic analysis
2430882 Support bbv_generation for the IP-PGV cell
2430400 Change Reff reporting to include all user-requested nodes
2429486 Self-Heat GUI improvements to include reference temperature and EM
2429481 Thermal analysis flow takes more than 48 hours to complete a single iteration
2429075 Failed to read RTL VCD
2428316 Web browser should start automatically
2426666 Need RLRP tracing based on the worst/best EIV tap/port for all instances
2424406 [Vector Profile] Enhancement to get worst window on each vector
2421784 Enhancement to overwrite the VCD logic state in the dynamic vector-based flow
2421163 validate_pg_library is not working correctly
2420985 Incorrect current waveform captured while using FSDB for PGV generation
2417248 Toggle rate differences between CPE and PM if set_default_switching_activity uses the _ratio options
2416806 Can Voltus provide di/dt in steady-state mode?
2415679 Voltus ERA flow inside Innovus errors out during generate_pg_library
2415465 User-specified current value is not used for domain-based rail analysis in the XP flow
2414534 Need debug report that lists invalid arcs
2414529 Incorrect TWF delay interpretation
2408111 Include Ilimit and polynomial equation in the EM attribute form
2400380 Generate multiple macro block LEFs and keep the block pin name by GDS2DEF
2399697 EM results filtering capability for the block ports
2399115 Simulation stops because of case sensitivity
2365472 Voltus extractor exits unexpectedly during rail analysis
2364613 Typo in power reporting
2364465 False EM violation in the AP layer
2360854 Narrow width resistance potentially causes false EM error
2360709 Provide an option to modify the PWL units in the current region file
2357897 'report_power' leaves huge text files after running
2357276 Voltus is not honoring the leakage power when provided through set_power
2355434 Dynamic voltage waveform loading takes nearly 20mins
2355346 Current peak distance is increasing period after period
2353562 set_db check_ac_limit_detailed true does not work
2352761 Macro output is being scheduled for pin with no timing
2349753 Distributed Power - rNetSwitchingActivity and rPinSwitchingActivity commands are missing
2349697 Error for set_power_data -format area if the net name contains slash
2346868 Update TCL to run SpeedEM and PowerDC from Voltus
2344868 Need enhancement for map_activity_file to inverse the duty for QN
2328239 Print TWF stats information in the Voltus log and power.missing_data.twf file
2323853 set_power cannot support block name power assignment
2309242 Cell viewer showed fly line in the EM view of 20.1 PGV, but detailed information in 19.1 PGV
2293267Give an option to combine reports without lighter version of power analysis
2288122 analyze_resistance: dump layer name and pin XY location in the output report
2280355 "Node Reff" value is "0" instead of "NA"
2277043 Enhancement to set the VU threshold value
2272900 Voltus XP reports 0.226kA with a set power of 4.5W
2271692 Need a new -current_generation_method that does both peak preservation as well as charge preservation in the dynamic current waveform
2267338 LibGen macro PGV generation exits unexpectedly
2259254 Voltus needs to include the unconnected instances to be present in the default rail ptiavg
2256440 Need additional enhancements to the itaputil utility
2250345 DGUI: Need some information about machine waiting/status/acquisition in the terminal and log
2246964 Die model flow uses very high disk memory
2241513 dynamic_switch_pattern { - - } is not honored with -no_propagation
2238671 Add the Stylus command for report_instances_missing_current_data
2209216 Support different dynamic power mode per DP block
2180593 set_power -ascii_power_file needs support for loading gzipped files
2173934 Enable RLRP analysis (layer-based resistance reporting) in the ESD B2C flow
2109507 Option to change the VSRC and node (VIA) size on the fly
1997150 Default unit change of em_conductor_unit and em_via_area_unit
1993851 Accurate supply current modeling for resistive shielding
1973563 Need to remove the warning message ‘No valid current data found to perform dynamic analysis’ when there are valid current regions
1964608 Rail needs to handle NA in pg_trigger during the VCD-based power-up analysis
1961552 Need an option to calculate path length with summing of all connected metal segments
1833148 ICT EM syntax support - ANTI_DERATE
August 09, 2022
Silicon signoff and verification (SSV) encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout. These steps report errors that require iterative and incremental fixes, also called engineering change orders (ECOs), ensuring the design integrity from an electrical and physical standpoint. All of Cadence’s signoff tools or capabilities are integrated in the Virtuoso platform, providing the same capabilities for mixed-signal and custom designs.
Knowledge and Learning
Learn about the latest Cadence offerings and solutions directly from our developers and experts. View interesting videos covering feature demos, troubleshooting information, flow launches, and more.
Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.
Owner: Cadence
Product Name: Silicon Signoff and Verification (SSV)
Version: 22.10.000 (Base Release) - 22.11.100-ISR1 *
Supported Architectures: x86_64
Website Home Page : www.cadence.com
Languages Supported: english
System Requirements: Linux **
Size: 23.6 Gb
Base_SSV22.10.000.lnx86
Hotfix_SSV22.11.000-CERTUS.lnx86
Hotfix_SSV22.11.100-ISR1.lnx86
Hotfix_SSV22.11.000-CERTUS.lnx86
Hotfix_SSV22.11.100-ISR1.lnx86
Supported OS and Platform Levels
================================
This build is based on the 2022 platform support matrix, linux only. From this release onwards RH7.4 is the minimum requirement and won't run on RH6.X.
![Cadence SSV Release Version 22.11.100]()
================================
This build is based on the 2022 platform support matrix, linux only. From this release onwards RH7.4 is the minimum requirement and won't run on RH6.X.
Cadence SSV Release Version 22.11.100
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Added by 3% of the overall size of the archive of information for the restoration
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![Cadence SSV Release Version 22.11.100]()
Added by 3% of the overall size of the archive of information for the restoration
No mirrors please
Cadence SSV Release Version 22.11.100
